Data entry keyboard apparatus includes a key switch array (18) in a keyboard unit (12) connected via a cable (14) to a tamper-resistant module (28) which contains control circuitry (16). The control circuitry (16) includes a random pattern generator (30) which generates successive random patterns, causing the selection of a single column and a random pattern of rows, thereby effecting the simulation of key actuations. An EXCLUSIVE-OR gating network (56a-56d) is effective to distinguish a genuine key actuation from simulated key actuations. The invention prevents the ascertainment of actuated keys by unauthorized tapping connections applied to the keyboard unit (12) or the cable (14).

Data entry keyboard apparatus

Debounce and lockout filters (20) include an input part (22) for receiving a plurality of input signals (V₁-VN) from switches (10), a microprocessor (24) and an output part (26). The filters (20) simultaneously process a plurality of input binary signals (V₁-VN) in parallel according to a sequence of mask values which individually adjust the filter response function for each of the individual filter channels (1-N). A multichannel filter (20) has a filter simultaneously filtering each input signal of a plurality of input signals (V₁-VN), the filter including a plurality of independent filter channels (1-N), each independent filter channel filtering a corresponding input signal (V) of the plurality of input signals to produce a corresponding output signal (F) of a plurality of output signals (F₁-FN). The multichannel filter (20) also has a mechanism for independently adjusting a filter response time (Figs. 5,15) of each independent filter channel.

Method and apparatus for debouncing signals

A synchronizer which samples and stores the synchronized data with a transparent latch instead of a flip-flop or similar device to avoid the long set-up times required by such devices. The synchronizer compares its input level to its output level. When they are found to be different because of an input data change, the difference is used to gate the system clock, which in turn gates the transparent latch to sample and store the changed input data level as the new data output level. Since the change in the input data gates the system clock which further gates the opening of the latch, the input data is essentially guaranteed to fulfill the latch set up time requirements. For the difficult case when the input data change occurs as the clock is changing states, a Schmitt trigger is inserted ahead of the latch gating input. The Schmitt trigger will either respond and provide a proper pulse width and magnitude to drive the latch without metastability, or it will pass a "runt pulse" and not respond to it. The latch gating input likewise will not respond to the "runt pulse" because of the pulse's insufficient duration or level. Thus, the Schmitt trigger acts as a matched filter to prevent metastability problems from any runt pulses.

High speed data synchronizer

A microcomputer for driving a resonant circuit includes a CPU for processing data, an input circuit for detecting an input signal and for transmitting it to the CPU, an output circuit for outputting an output signal from the CPU to the resonant circuit, and attenuation device for attenuating oscillation in the resonant circuit after the output signal from the CPU is turned off. In a non-contact IC card the resonant circuit is an antenna for sending and receiving data to and from the outside without contact.

Microcomputer circuit for attenuating oscillations in a resonant circuit by reversing phase and feeding back resonant circuit output oscillation voltage

A variable frequency clock generator provides complementary phase clock signals for a microprocessor at a selectable one of a plurality of frequencies. The outputs may be dynamically switched between any of the frequencies so that every cycle of the phase clock signals has a duration at least as great as the cycle duration of the highest frequency.

An apparatus for providing a clock signal for a microprocessor at a selectable one of a plurality of frequencies and for dynamically switching between any of said plurality of frequencies

An improved debouncer circuit is disclosed for providing debounced, synchronously clocked digital signals from a single-throw switch, as for instance, of the momentary contact type. A signal, variable between two logic levels, is provided by the switch for input to the debouncer circuitry. That input signal is applied as one input to an EXCLUSIVE OR gate, the other input to that gate being fed back from the Q output terminal of an output data latch having complementary Q and Q* output terminals. A signal representing the Q* output terminal of the data latch is connected to the D input of that latch such that a synchronous latch clocking signal appearing at the clock input of the output data latch serves to toggle the states of the Q and Q* output terminals. The signal appearing at either one of the output terminals Q, Q* of the output data latch may be used as the debounced signal provided to other circuitry, depending upon signal polarity needs. The clocking signal which toggles the output data latch is the output of a NAND gate. The inputs to the NAND gate include one phase of a two-phase synchronous clock signal, the output of the EXCLUSIVE OR gate, and the signal from the Q output of a second data latch. The second data latch is clocked by the other phase of the two-phase synchronous clock. The D input of the second data latch is connected to the output of an AND gate, with the inputs to the AND gate being provided by the O* output of the second data latch and by the output of the EXCLUSIVE OR gate.

William M. Floyd

Papers

Debounce circuit providing synchronously clocked digital signals