Process gas discharged from a bypass pipe to a gas exhaust system can be prevented from diffusing back to the inside of a process chamber without having to install a dedicated vacuum pump at the downstream side of the bypass pipe. The substrate processing apparatus includes a process chamber accommodating a substrate, a gas supply system supplying process gas from a process gas source to the process chamber for processing the substrate, a gas exhaust system configured to exhaust the process chamber, two or more vacuum pumps installed in series at the gas exhaust system, and a bypass pipe connected between the gas supply system and the gas exhaust system. The most upstream one of the vacuum pumps is a mechanical booster pump, and the bypass pipe is connected between the mechanical booster pump and the rest vacuum pumps located at a downstream side of the mechanical booster pump.

Substrate Processing Apparatus

Energy storage systems (ESSs) play a very important role in recent years. Flywheel is one of the oldest storage energy devices and it has several benefits. Flywheel Energy Storage System (FESS) can be applied from very small micro-satellites to huge power networks. A comprehensive review of FESS for hybrid vehicle, railway, wind power system, hybrid power generation system, power network, marine, space and other applications are presented in this paper. There are three main devices in FESS, including machine, bearing, and Power Electronic Interface (PEI). Furthermore, advantages and disadvantages all of them have been presented. In addition a brief review of new and conventional power electronic converters used in FESS, have been discussed. Finally, practical ways to develop this technology in the future are presented.

A comprehensive review of Flywheel Energy Storage System technology

Numerical modeling of superconductors is widely recognized as a powerful tool for interpreting experimental results, understanding physical mechanisms, and predicting the performance of high-temperature-superconductor (HTS) tapes, wires, and devices. This is particularly true for ac loss calculation since a sufficiently low ac loss value is imperative to make these materials attractive for commercialization. In recent years, a large variety of numerical models, which are based on different techniques and implementations, has been proposed by researchers around the world, with the purpose of being able to estimate ac losses in HTSs quickly and accurately. This paper presents a literature review of the methods for computing ac losses in HTS tapes, wires, and devices. Technical superconductors have a relatively complex geometry (filaments, which might be twisted or transposed, or layers) and consist of different materials. As a result, different loss contributions exist. In this paper, we describe the ways of computing such loss contributions, which include hysteresis losses, eddy-current losses, coupling losses, and losses in ferromagnetic materials. We also provide an estimation of the losses occurring in a variety of power applications.

Computation of Losses in HTS Under the Action of Varying Magnetic Fields and Currents

Embodiments related to managing the process feed conditions for a semiconductor process module are provided. In one example, a gas channel plate for a semiconductor process module is provided. The example gas channel plate includes a heat exchange surface including a plurality of heat exchange structures separated from one another by intervening gaps. The example gas channel plate also includes a heat exchange fluid director plate support surface for supporting a heat exchange fluid director plate above the plurality of heat exchange structures so that at least a portion of the plurality of heat exchange structures are spaced from the heat exchange fluid director plate.

Process feed management for semiconductor substrate processing

The present invention relates to a process and system for depositing a thin film onto a substrate. One aspect of the invention is depositing a thin film metal oxide layer using atomic layer deposition (ALD).

Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species

A gas supply device may include a first gas supply member that may be disposed in a chamber and around a substrate loaded in the chamber. The first gas supply member may include nozzles for providing a gas onto the substrate. A second gas supply member that may provide the gas supplied from at least one gas supply line to the first gas supply member.

Gas supply device and apparatus for processing a substrate

Development of a 600 kJ Superconducting Magnetic Energy Storage (SMES) system is in progress by Korean Electric Research Institute (KERI). High-temperature superconducting (HTS) wires are going to be used for the winding of the system. The design of the HTS windings for the system is presented in this paper. We considered BSCCO-2223 wire for the HTS windings. The operating temperature of the winding was decided to be 20 K which will be accomplished by conduction cooling method using cryo-coolers. Auto-Tuning Niching Genetic Algorithm was adopted for an optimization method of the HTS magnets in the SMES system. The objective function of the optimal process was minimizing the total amount of the HTS wire. We also estimated the AC loss which can be generated in the discharge period. These HTS windings are going to be applied to the SMES system whose purpose is the stabilization of the power grid

Design of HTS Magnets for a 600 kJ SMES

A time-to-digital converter (TDC) is a key element for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. To build high-resolution TDCs, many researchers have focused on minimizing the unit delay of quantization. Vernier delay-line-based TDCs [1] are a good example. Their performance, however, is limited by delay variation and random mismatch among delay cells, unless additional error correction or external control are applied. A time-domain successive-approximation scheme [2] could be an option to achieve high resolution but it consumes too much power and area to generate precisely tuned delay cells. In another case, time-amplifier-based multi-step TDCs [3,4] that can alleviate the requirement on the minimum unit delay of the quantization by time-difference amplification, may be an attractive option. However these tend to be power-hungry or to require additional calibration circuitries due to the inaccuracy and PVT vulnerability of the time amplifier or time register. In this paper, we present a simple, low-power, and PVT-variation-tolerant TDC architecture without any calibration, using stochastic phase interpolation and 16x spatial redundancy.

15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology

A phase-locked loop (PLL) integrated circuit includes an oscillation control voltage generating circuit therein. The oscillation control voltage generating circuit is configured to pre-scale an output current of a charge pump therein to a first level in response to disposing the PLL integrated circuit into a pre-calibration mode of operation. The oscillation control voltage generating circuit may be responsive to an input signal (e.g., SIN) and a feedback signal (e.g., SFEED), and the magnitude of the first level of the charge pump current during the pre-calibration mode of operation may be independent of any phase difference between the input signal and the feedback signal.

Phase-Locked-Loop Circuit Having a Pre-Calibration Function and Method of Pre-Calibrating the Same

A 1 MVA single phase high temperature superconducting (HTS) transformer was manufactured and tested. The rated voltage of primary and secondary of HTS transformer are 22.9 kV and 6.6 kV respectively. BSCCO-2223 HTS tape was used for HTS windings of 1 MVA HTS transformer. In order to reduce AC loss generated in the HTS winding, the concentrically arranged winding was adopted to 1 MVA HTS transformer. Single HTS tape for primary windings and 4 parallel HTS tapes for secondary windings were used considering the each rated current of the HTS transformer. A core of HTS transformer was fabricated as a shell type core made of laminated silicon steel plate. And a GFRP cryostat with a room temperature bore was also manufactured. The characteristic tests such as no load test, short circuit test and several insulation tests were performed at 65 K using sub-cooled liquid nitrogen. Through these test results, the validity of design of HTS transformer was ascertained.

Woo-Seok Kim

Papers

Gas supply device and apparatus for processing a substrate

Design of HTS Magnets for a 600 kJ SMES

15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology

Phase-Locked-Loop Circuit Having a Pre-Calibration Function and Method of Pre-Calibrating the Same

Characteristic tests of a 1 MVA single phase HTS transformer with concentrically arranged windings