The invention discloses a scan drive circuit and a liquid crystal display device. The scan drive circuit includes a forward and reverse scan module, a pull-up keeping module, an input module, a control module and an output module. The forward and reverse scan module outputs forward and reverse scan drive signals. The pull-up keeping module is connected to the forward and reverse scan module, receives selection signals output from the forward and reverse scan module, and pulls up pull-down control signal points. The input module is connected to the forward and reverse scan module and the pull-up keeping module, and receives superior-stage clock signals to charge pull-up control signal points. The control module is connected to the pull-up keeping module, and receives current-stage clock signals to control the pull-up keeping module. The output module is connected to the pull-up keeping module and the control module, and outputs the scan drive signals to a scan line to transmit the scan drive signals to a pixel unit. In this way, the stability of the scan drive circuit is ensured.

Scan drive circuit and liquid crystal display device with the same

The invention discloses a trigger and an integrated circuit, which are used for reducing the probability of metastable phenomena of the trigger. The trigger comprises a first latch, a second latch, adelay unit, a detection unit, a switching unit and a third latch. The delay unit is used for delaying the first clock signal and outputting a second clock signal; the first latch is used for latchingor outputting the data signal according to the second clock signal; the second latch is used for latching or outputting the data signal according to the first clock signal; the detection unit is usedfor detecting whether the first latch or the second latch is in a metastable state or not and outputting a control signal to the switching unit based on a detection result; the switching unit is usedfor selectively outputting an output signal of the first latch or an output signal of the second latch according to the control signal; and the third latch is used for latching or outputting the output signal of the switching unit.

Trigger and integrated circuit

A D flip-flop capable of preventing metastability comprises a potential control circuit (100) and, a first phase inverter (10), a first latch unit (20), a second phase inverter (30), and a second latch unit (40) that are sequentially coupled The potential control circuit (100) is used to control, when an input end (A) and an output end (B) of the first latch unit (20) are at the same level, the input end (A) and the output end (B) of the first latch unit (20) to be at a low level and a high level, respectively, or to be at a high level and a low level, respectively When the input end (A) and the output end (B) of the first latch unit (20) are at the same level, the potential control circuit (100) is used to forcibly control the input end (A) and the output end (B) of the first latch unit (20) to be at different levels, thereby breaking a deadlock state in which the input end (A) and the output end (B) of the first latch unit (20) are at the same level, and preventing metastability

D flip-flop capable of preventing metastability

A flip-flop (700) and an integrated circuit, wherein same are used to reduce the probability of the occurrence of the phenomenon of metastability of a flip-flop. The flip-flop (700) comprises: a first latch (701), a second latch (702), a delay unit (703), a detection unit (704), a switching unit (705) and a third latch (706), wherein the delay unit (703) is used to delay a first clock signal and then output a second clock signal; the first latch (701) is used to latch or output a data signal according to the second clock signal; the latch (702) is used to latch or output the data signal according to the first clock signal; the detection unit (704) is used to detect whether the first latch (701) or the second latch (702) is in a metastable state, and output a control signal to the switching unit (705) based on a detection result; the switching unit (705) is used to choose, according to the control signal, to output an output signal of the first latch (701) or an output signal of the second latch (702); and the third latch (706) is used to latch or output an output signal of the switching unit (705).

Flip-flop and integrated circuit

The invention relates to a piece of metastable state reducing D flip-flop equipment comprising a flip-flop body which is provided with a signal input port. The metastable state reducing D flip-flop equipment is characterized in that the signal input port is connected with a phase inverter, and the output end of the phase inverter is connected with a differential assembly. Meanwhile, the differential assembly is provided with an output port, the differential assembly is composed of at least two identical latches (a master latch and a slave latch) which are connected, and the phase inverter converts a secondary differential output signal into single-end output. Therefore, the occupied area is reduced, and the overall stability of operation is improved. Moreover, there is no need to add an additional feedback branch and external voltage bias for different processes, and the equipment can be conveniently used in various processes through appropriate design.

Wu Xin

Papers

Metastable state reducing D flip-flop equipment