The fast Hartley transform (FHT) is similar to the Cooley-Tukey fast Fourier transform (FFT) but performs much faster because it requires only real arithmetic computations compared to the complex arithmetic computations required by the FFT. Through use of the FHT, discrete cosine transforms (DCT) and discrete Fourier transforms (DFT) can be obtained. The recursive nature of the FHT algorithm derived in this paper enables us to generate the next higher order FHT from two identical lower order FHT's. In practice, this recursive relationship offers flexibility in programming different sizes of transforms, while the orderly structure of its signal flow-graphs indicates an ease of implementation in VLSI.

/pdf/the-fast-hartley-transform-algorithm-6o7hxywnqf.pdf

The Fast Hartley Transform Algorithm

We briefly review some key scientific and parallel processing issues in a selection of some 84 existing applications of parallel machines. We include the MIMD hypercube transputer array, BBN Butterfly, and the SIMD ICL DAP, Goodyear MPP and Connection Machine from Thinking Machines. We use a space-time analogy to classify problems and show how a division into synchronous, loosely synchronous and asynchronous problems is helpful. This classifies problems into those suitable for SIMD or MIMD machines and isolates the asynchronous class as that for which major uncertainties as to possible parallelism exist. Interestingly about half of the scientific applications run excellently on SIMD machines with the other half able to take especial advantage of the MIMD architecture.

What have we learnt from using real parallel machines to solve real problems

A parallel, pipelined architecture for calculating the fast Hartley transform (FHT) is discussed. Hardware implementation of the FHT introduces two challenges: retrograde indexing and data scaling. A novel addressing scheme that permits the fast computation of FHT butterflies is proposed, and a hardware implementation of conditional block floating point scaling that reduces error due to data growth with little extra cost is described. Simulations reveal a processor capable of transforming a 1 K-point sequence in 170 mu s using a 15.4 MHz clock. >

Calculating the FHT in hardware

In most convolution neural networks (CNNs), downsampling hidden layers is adopted for increasing computation efficiency and the receptive field size. Such operation is commonly so-called pooling. Maximation and averaging over sliding windows (max/average pooling), and plain downsampling in the form of strided convolution are popular pooling methods. Since the pooling is a lossy procedure, a motivation of our work is to design a new pooling approach for less lossy in the dimensionality reduction. Inspired by the Fourier spectral pooling(FSP) proposed by Rippel et. al. [1], we present the Hartley transform based spectral pooling method in CNNs. Compared with FSP, the proposed spectral pooling avoids the use of complex arithmetic for frequency representation and reduces the computation. Spectral pooling preserves more structure features for network's discriminability than max and average pooling. We empirically show that Hartley spectral pooling gives rise to the convergence of training CNNs on MNIST and CIFAR-10 datasets.

Hartley Spectral Pooling for Deep Learning

This paper presents a novel discrete Hartley transform based VLSI architecture for quickly computing the N-point discrete Fourier transform (DFT) and its inverse (IDFT), where N is a power of two. The architecture consists of one real multiplier, three real adders, five special memory units, and some simple logic circuits. It can evaluate, in average, one DFT sample every log/sub 2/N+2 clock cycles or one IDFT sample every log/sub 2/N+1 clock cycles. Under 0.6 /spl mu/m CMOS technology, the proposed design consumes chip area about 4838/spl times/4032 /spl mu/m/sup 2/ to reach a throughput of 4 M DFT samples per second or 3.6 M IDFT samples per second for the case of N=512. Such area-time performance shows that it is rather attractive for use in discrete multitone based ADSL transceivers.

A novel DHT-based FFT/IFFT processor for ADSL transceivers

The Fast Hartley Transform is a promising alternative to the Fast Fourier Transform when the processed data are real numbers. The hypercube implementation of the FHT is largely dependent on the way the computation is partitioned. A partitioning algorithm is presented which generates evenly-loaded tasks on each node and demands only a regular communication topology — the Hartley graph. Mapping from the Hartley graph to the Gray graph (binary n-cube) is straightforward, since the Hartley graph has a similar structure as the Gray graph. However, the communication is not always between the nearest neighbors and thus may take some extra time. Moreover, the slowness of the communication in the presently available architectures imposes a limitation on the speedup when a large number of processors are used.

X. Lin

Papers

The fast Hartley transform on the hypercube multiprocessors