Recovery from compressed measurements using Sparsity Independent Regularized Pursuit

This paper presents a System on Chip (SoC) implementation of the standard Orthogonal Matching Pursuit (OMP) algorithm using matrix partition and Modified Cholesky factorization techniques. A fixed-point optimized hardware Intellectual Property (IP) of the OMP algorithm is designed using a high-level synthesis (HLS) tool. The execution time of the optimized fixed-point hardware IP for different sparsity is compared with the equivalent fixed-point and floating-point realization on the Zynq-7000 Field Programmable Gate Array (FPGA). Intel senor data is used for verifying the functionality of the SoC design. The experiment is carried out for signal length (N), compressed signal length (M) as 256 and 84 respectively with different sparsity factor (K) as 5, 10 and 15. The acceleration factor of 70 and 73 is achieved for the fixed-point and floating-point software realization of the OMP algorithm, respectively.

System on Chip Implementation of Low Complex Orthogonal Matching Pursuit Algorithm on FPGA

Sparse recovery algorithms are integral to compressed sensing (CS) as they facilitate the reconstruction of higher dimensional signals from sub-Nyquist measurements. Although Orthogonal Matching Pursuit (OMP) has been ubiquitously adopted in hardware implementations to curb the computational complexity of CS recovery, increasing sparsity levels incur higher reconstruction costs. Sparsity independent regularized pursuit (SIRP) is a recent algorithm that employs parallel index selection and regularization to curtail the number of iterations required to reconstruct the signal and thereby enhance the reconstruction speed. This paper proposes a novel reformulation of the SIRP algorithm from the hardware perspective, incorporating a cheaper regularization strategy and a modified Gram-Schmidt (MGS) based incremental QR decomposition (QRD) approach. The proposed design incorporates an iterative QRD architecture with feedback circuitry to exploit the parallelism of the triangularization step in MGS. Additionally, a fast inverse square block circumvents the need for parallel divider blocks giving considerable hardware and latency savings. The design reuses the iterative QRD block to implement the interdependent computations of the algorithm by sophisticated scheduling techniques. The proposed implementation on a Xilinx Virtex Ultrascale FPGA can recover 1024-dimensional signals from 25% measurements within $77~\mu \text{s}$ , which translates to a 37% reduction in processing cycles from state-of-art.

FPGA Implementation of Sparsity Independent Regularized Pursuit for Fast CS Reconstruction

The power system expansion and the integration of technologies, such as renewable generation, distributed generation, high voltage direct current, and energy storage, have made power system simulation challenging in multiple applications. The current computing platforms employed for planning, operation, studies, visualization, and the analysis of power systems are reaching their operational limit since the complexity and size of modern power systems results in long simulation times and high computational demand. Time reductions in simulation and analysis lead to the better and further optimized performance of power systems. Heterogeneous computing—where different processing units interact—has shown that power system applications can take advantage of the unique strengths of each type of processing unit, such as central processing units, graphics processing units, and field-programmable gate arrays interacting in on-premise or cloud environments. Parallel Heterogeneous Computing appears as an alternative to reduce simulation times by optimizing multitask execution in parallel computing architectures with different processing units working together. This paper presents a review of Parallel Heterogeneous Computing techniques, how these techniques have been applied in a wide variety of power system applications, how they help reduce the computational time of modern power system simulation and analysis, and the current tendency regarding each application. We present a wide variety of approaches classified by technique and application.

A Review of Parallel Heterogeneous Computing Algorithms in Power Systems

Implementing sparse estimation efficiently in digital hardware is crucial for real-time applications. For such an implementation one typically favours lightweight iterative algorithms. This not only keeps the complexity low, but also allows a fine-granular tuning of the performance/complexity trade-off. Recently, algorithms based on Linearized Bregman Iterations (LBI) have shown to be very feasible for low complexity digital hardware implementation. An alternative approach would be to use cyclic coordinate descent (CCD) algorithms. However, the state-of-the-art formulation of sparse cyclic coordinate descent has properties preventing an efficient hardware implementation. In this work, we propose variations of cyclic coordinate descent, specifically tailored for digital efficient hardware implementation. These modifications allow cyclic coordinate descent algorithms to be competitive in a hardware implementation compared to the implementation efficient Linearized Bregman iteration algorithms. We show simulation results for different sparse estimation use-cases demonstrating the capabilities of both methods. We also identify scenarios where our CCD approach allows to obtain the same performance with less complexity than LBI.

Implementing Sparse Estimation: Cyclic Coordinate Descent vs Linearized Bregman Iterations

Compressive sensing (CS) is a novel signal processing technology to reconstruct the sparse signal at sub-Nyquist rate. Orthogonal matching pursuit (OMP) is one of the most widely used signal reconstruction algorithms. However, the least square problem (LSP) in OMP algorithm limits its performance. This paper presents a fast CS reconstruction algorithm implemented on field-programmable gate array (FPGA) using OMP. The proposed algorithm adopts an incremental QR decomposition (QRD) method to efficiently solve the LSP. The incremental QRD is further optimized to eliminate the square root operation to facilitate hardware implementation. The proposed architecture avoiding the complex square root unit mainly consists of some more basic computing units, where the computing process is broken down into several simple operations to map to the corresponding hardware for pipelining. The proposed implementation based on Xilinx Kintex-7 FPGA exploits the parallelism by a well-planned workload schedule and reaches an optimal tradeoff between the latency and frequency. The experimental results demonstrate that the proposed architecture can run at a frequency of 210 MHz with a reconstruction time of 238 $\mu \text{s}$ for 36-sparse 1024-length signal, which improves the signal reconstruction speed by $1.43\times $ compared to the state-of-the-art implementations.

An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition

LU decomposition is widely used in the field of numerical analysis and engineering to solve large-scale sparse linear equations. The complex data dependency makes it difficult to parallelize the LU decomposition. In this paper, an architecture with an efficient cache for parallel sparse LU decomposition using FPGA is proposed. The proposed architecture is based on the Gilbert-Peierls (G-P) algorithm. By using the elimination graph, we find the column dependency of the LU decomposition. It is thus possible to exploit the parallelism. Through a dependency table, a simple but efficient cache strategy and its corresponding architecture are proposed. The proposed cache strategy avoids the cache miss and reduces the size of cache used to store all the intermediate data on chip. The experiment demonstrates that, our design can achieve speedup of 2.85x–10.27x, compared with UMFPACK running on general purpose processors. The cache size can be reduced by 50.93% on average with the proposed cache strategy.

Xiang Ge

Papers

An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition

Parallel sparse LU decomposition using FPGA with an efficient cache architecture