Analytical model for asymmetric single-electron tunneling transistors (SETTs), in which resistance and capacitance parameters of source/drain junctions are not equal, has been developed. The model is based on the steady-state master equation, takes only the two most-probable charging states into account, and is therefore very simple. Even so, it can accurately reproduce the peculiar behaviors of an asymmetric SETT, such as the skew in the drain current-gate voltage characteristics and the Coulomb staircase in the drain current-drain voltage characteristic. Analytical expressions for the charge in the Coulomb island and the capacitance components of the SETT are also derived according to the same scheme, and it is demonstrated that the model can precisely describe the various aspects of the SETT behavior.

A compact analytical model for asymmetric single-electron tunneling transistors

Downscaling of the devices of integrated circuits (ICs) has reached the verge of nanometer scale. On this scale, new phenomena of a quantum nature are starting to appear in ICs. The necessity of the development of new tools for studding the behavior of such circuits that take into account these phenomena is evident. For this reason, a new system for the design and simulation of single electron circuits called SECS has been developed. The operation of single electron circuits is based on the tunneling effect. The stochastic nature due to tunneling is incorporated in the simulation of single electron circuits using the Monte Carlo method. The novelty of the SECS system is that it provides the behavior of single electron circuits in an actual time scale, making thus easier and more complete the study of the phenomena that take place at an arbitrary single electron circuit.

SECS: A New Single-Electron-Circuit Simulator

In this paper, we propose a diagrammatic approach to single-electron spintronics and develop a new analytical model for ferromagnetic single electron transistors (FSETs) using the proposed approach. Before this, we have reported an analytical model for FSET which was the only analytical model for FSETs introduced. It was a zero temperature one and was based on orthodox theory by solving several long equations simultaneously such that if one deals with a large system which includes several devices, number of complex equations is increased significantly. Here, the new proposed analytical model uses a much simpler diagrammatic approach and less calculation compared to the existing analytical model. We have used the model for two types of island material based on that spin splitting be negligible or not. This model provides a clear physical insight into single-electron spintronics and has been verified against the existing analytical model and numerical simulations. A good agreement has been shown and the model validity has been established.

A diagrammatic approach to single-electron spintronics and a new analytical model for ferromagnetic single-electron transistors

Rhombic Coulomb diamonds are clearly observed in a chemically anchored Au nanoparticle single-electron transistor. The stability diagrams show stable Coulomb blockade phenomena and agree with the theoretical curve calculated using the orthodox model. The resistances and capacitances of the double-barrier tunneling junctions between the source electrode and the Au core (R1 and C1, respectively), and those between the Au core and the drain electrode (R2 and C2, respectively), are evaluated as 4.5 MΩ, 1.4 aF, 4.8 MΩ, and 1.3 aF, respectively. This is determined by fitting the theoretical curve against the experimental Coulomb staircases. Two-methylene-group short octanedithiols (C8S2) in a C8S2/hexanethiol (C6S) mixed self-assembled monolayer is concluded to chemically anchor the core of the Au nanoparticle at both ends between the electroless-Au-plated nanogap electrodes even when the Au nanoparticle is protected by decanethiol (C10S). This is because the R1 value is identical to that of R2 and corresponds to the tunneling resistances of the octanedithiol chemically bonded with the Au core and the Au electrodes. The dependence of the Coulomb diamond shapes on the tunneling resistance ratio (R1/R2) is also discussed, especially in the case of the rhombic Coulomb diamonds. Rhombic Coulomb diamonds result from chemical anchoring of the core of the Au nanoparticle at both ends between the electroless-Au-plated nanogap electrodes.

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Rhombic Coulomb diamonds in a single-electron transistor based on an Au nanoparticle chemically anchored at both ends

The clock distribution network and the generation circuitry are critical components of current synchronous digital systems and are known to consume more than a quarter of the power budget of existing microprocessors. A high-level clock energy model that captures both the dynamic and leakage power components is formulated. The validation results show an average deviation within 506 of circuit-level simulations. 
Further, Phased Locked Loops (PLLs), which have been generally used in clock generation, are also crucial for the implementation of Dynamic Voltage Scaling (DVS) mechanisms employed in emerging power conscious processor designs. In order to devise architectural and compiler driven optimizations that exploit the dynamic frequency voltage scaling features, accurate models that capture the performance and power characteristics of the PLL are essential. In addition, many emerging System-on-a-Chip (SOC) designs use multiple PLLs on the same die making it important to estimate the contribution of the PLL to the overall system power. A PLL energy and timing model that accurately estimates the power consumption during both lock and lock-acquisition states is also formulated. The applicability of PLLs as voltage regulators in support of leakage reduction by supply gating is briefly discussed. 
The complete clock energy model is incorporated into a cycle-accurate energy simulator for an embedded architecture. This framework is used to study and quantify the influence on clock energy of several architectural-level decisions and their relative impact on the overall system power. These design choices include various cache architectures and clock gating at different levels (top-level distribution network functional unit and gate level). From the software perspective, the influence on clock energy of power-aware memory-oriented compiler optimizations is assessed. 
Finally, the model is used to predict the role that the clock will have in the total power budget of future designs while carefully capturing the impact of technology scaling. It is shown that as long as leakage power is kept under control, clock power will remain a significant contributor to the total system power.

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Clock network and phase-locked loop power estimation and experimentation

Single-electron transistor analyticI–Vmodel for SPICE simulations

A low power CMOS clock buffer based on charge recycling technique is presented. To accomplish the charge recycling process and avoid introducing the extra short circuit current during the recycling phase, an extra switching circuit and control signal are utilized to keep inverters momentarily tri-state. The feasibility of this design and its improved power efficiency are demonstrated by simulations.

Xiaohui Wang

Papers

Single-electron transistor analyticI–Vmodel for SPICE simulations

A low power charge-recycling CMOS clock buffer