The time and temperature dependence of Stress-Induced-Voiding below and in copper VIA's with a diameter of 80nm integrated in a k=2.5 material was studied. The focus was on the early phase of the voiding process. To accelerate the degradation, test structures with big metal plates below and/or above the VIA were used. We found two degradation mechanisms in which one dominated below and the other dominated above a certain temperature. The first mechanism has an activation energy of 0.9eV and is the result of interface-diffusion driven by a stress-gradient. This mechanism was more pronounced below the VIA, but was significant in the VIA as well. The second mechanism has an activation energy of 1.2eV, which is argued to be driven by grain boundary diffusion due to a vacancy gradient in and above the VIA. To explain both mechanisms, an addition to the traditional stress-creep model is proposed and fits our data well. Additionally, it is discussed that VIA's connected to the center of big metal plates above and below the VIA are less susceptible to SIV compared to VIA's connected to line ends either below or on top of the VIA. We support our argumentation and analytical modeling with Finite Element Modeling.

Time and temperature dependence of early stage Stress-Induced-Voiding in Cu/low-k interconnects

The influence of residual vacancy concentrations and stress gradients on electromigration both in the metal layer below and above copper via's with a diameter of 90nm integrated in low-k materials has been investigated. Variations in stress gradients and vacancy concentrations were created by applying different post-plating anneal conditions. The impact of these variations was quantified based on high temperature storage tests both at the optimum stress-induced-voiding temperature and around the copper stress free temperature. By linking the results from these high temperature storage tests to electromigration data, we observe residual vacancy concentrations contribute more to upstream electromigration, while downstream electromigration is more vulnerable to residual stress gradients.

Electromigration and stress-induced-voiding in dual damascene Cu/low-k interconnects: a complex balance between vacancy and stress gradients

This paper will start by comparing brainpsilas connectivity (based on different analyses of neurological data) versus well-known network topologies (originally used in massively parallel super-computers), in view of the latest interpretation of Rentpsilas rule. These will reveal that the brain is in very good agreement with Rentpsilas rule average growth rate. With respect to classical network topologies, the crossbar (only for quite small sizes) and the cube connected cycles (for a wider range) look like promising contenders (for the brain), while in fact any network topology falls short of properly mimicking brainpsilas connectivity. That is why, we will go on exploring hybrid (hierarchical) combination of two network topologies, allowing us to identify those (hybrid network topologies) which could closely emulate brainpsilas connectivity (as well as the particular ranges where this is happening).

Xiaoling He

Papers

Electromigration and Stress Voiding of Cu/low-k Semiconductor Interconnects—65 nm Interconnect Technology and Beyond