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Xiaying Wang

Researcher at ETH Zurich

Publications -  26
Citations -  403

Xiaying Wang is an academic researcher from ETH Zurich. The author has contributed to research in topics: Computer science & Memory footprint. The author has an hindex of 6, co-authored 20 publications receiving 129 citations.

Papers
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Journal ArticleDOI

FANN-on-MCU: An Open-Source Toolkit for Energy-Efficient Neural Network Inference at the Edge of the Internet of Things

TL;DR: A FANN-on-MCU, an open-source toolkit built upon the fast artificial neural network (FANN) library to run lightweight and energy-efficient neural networks on microcontrollers based on both the ARM Cortex-M series and the novel RISC-V-based parallel ultralow-power (PULP) platform is presented.
Posted Content

EEG-TCNet: An Accurate Temporal Convolutional Network for Embedded Motor-Imagery Brain-Machine Interfaces

TL;DR: This paper proposes EEG-TCNet, a novel temporal convolutional network (TCN) that achieves outstanding accuracy while requiring few trainable parameters, which makes it suitable for embedded classification on resource-limited devices at the edge.
Proceedings ArticleDOI

An Accurate EEGNet-based Motor-Imagery Brain–Computer Interface for Low-Power Edge Computing

TL;DR: In this paper, the authors presented an accurate and robust embedded motor-imagery brain-computer interface (MI-BCI) based on EEGNet, which matches the requirements of memory footprint and computational resources of low-power microcontroller units (MCUs), such as the ARM Cortex-M family.
Proceedings ArticleDOI

EEG-TCNet: An Accurate Temporal Convolutional Network for Embedded Motor-Imagery Brain–Machine Interfaces

TL;DR: In this paper, a novel temporal convolutional network (TCN) was proposed for embedded classification on resource-limited devices at the edge, which achieved state-of-the-art performance on the BCI Competition IV-2a dataset.
Posted Content

An Accurate EEGNet-based Motor-Imagery Brain-Computer Interface for Low-Power Edge Computing

TL;DR: This paper presents an accurate and robust embedded motor-imagery brain–computer interface (MI-BCI), based on EEGNet, that matches the requirements of memory footprint and computational resources of low-power microcontroller units (MCUs), such as the ARM Cortex-M family.