The invention discloses a silicon-based near-infrared single photon avalanche diode detector, and belongs to the technical field of photoelectric detection. The single photon avalanche diode detectorcomprises a P-type epitaxial layer arranged above a P-type substrate, wherein the P-type substrate and the P-type epitaxial layer are provided with an N+ buried layer region therebetween, deep P wellregions are symmetrically arranged on the N+ buried layer region, a deep P well region is arranged on the N+ buried layer region at the central position, and an avalanche region is formed between thedeep P well region and the N+ buried layer region. According to the single photon avalanche diode detector, the deep avalanche region is formed between the deep P well and the N+ buried layer, the lightly-doped and uniformly distributed P-type epitaxial layer is utilized as a virtual protection ring at the same time to improve the near-infrared photon detection efficiency, the size of the device is reduced, and the dark counting noise is reduced. The manufacturing method can carry out manufacturing based on the standard silicon-based process, and has the advantages of low cost, high integration, low power consumption, near-infrared detection capability and the like.

Silicon-based near-infrared single photon avalanche diode detector and manufacturing method thereof

The invention belongs to the field of semiconductor photoelectric detectors, and particularly relates to an anti-radiation near-infrared focal plane detector and a manufacturing method. The detector comprises a detector array chip and a CMOS reading circuit, wherein the detector array chip is connected with the CMOS reading circuit through an indium column; a pixel area of the detector array chipis sequentially composed of an effective pixel, a dummy pixel and a redundant pixel from the center to the periphery. According to the invention, the dummy pixel is shielded by means of a metal shielding layer so as to enable the dummy pixel not to output a photo-generated signal; and compensation current is provided by utilizing the dummy pixel, and rising dark current of the effective pixels after irradiation is shunted. The detector is simple in structure, the feasibility of process manufacturing is considered, and the problem of performance parameter degradation of the near-infrared focalplane detector in the space irradiation environment can be effectively solved.

Anti-radiation near-infrared focal plane detector and manufacturing method

The invention discloses a photoelectric amplification circuit. The photoelectric amplification circuit comprises an amplifier, a first resistor, at least two first transistors and a current control module, the first resistor is connected between the first input end and the output end of the amplifier, the first input end of the amplifier is connected with a photodiode, and the second input end ofthe amplifier is connected with a reference voltage; each first transistor is connected in parallel between a first power supply and the first input end of the amplifier; the channel width-to-length ratios of the first transistors are different; and the controller is connected with the two ends of the first resistor and the grid electrodes of the first transistors respectively, and is used for controlling to turn on at least one first transistor according to the voltage at the two ends of the first resistor, and the channel width-to-length ratio of the first transistor which is turned on lateris greater than the channel width-to-length ratio of the first transistor which is turned on first. The photoelectric amplification circuit disclosed by the invention realizes the effects of high sensitivity, strong anti-interference capability and high signal-to-noise ratio.

Photoelectric amplification circuit

The invention relates to a time interval measurement device and method based on multi-channel interpolation, and particularly relates to the technical field of high-resolution time interval measurement. The time interval measurement device based on the multi-channel interpolation comprises a tested gate generation unit, wherein the tested gate generation unit is connected with a counting unit, a front-error extraction unit and a rear-error extraction unit; the counting unit, the front-error extraction unit and the rear-error extraction unit are connected with the same clock unit; the front-error extraction unit is connected with a first multi-path distribution unit; the first multi-path distribution unit is connected with a plurality of front interpolation units; the rear-error extractionunit is connected with a second multi-path distribution unit, and the second multi-path distribution unit is connected with a plurality of rear interpolation units; and the counting unit, the front interpolation units and the rear interpolation units are connected with an arithmetic unit. According to the scheme, multi-channel interpolation is adopted for simultaneous measurement, then an averagecalculation method is carried out, and the measurement resolution is the original resolution (N is the number of interpolation channels).

Time interval measurement device and method based on multi-channel interpolation

The invention discloses a single-photon avalanche diode with a low dark counting rate and a manufacturing method thereof, which belong to the technical field of single-photon detection. The single-photon avalanche diode comprises a P-type epitaxial layer arranged on a substrate; an N-type isolation region is arranged in the P-type epitaxial layer; N well regions are symmetrically arranged on the two sides of the N-type isolation region; an N + heavily doped region is coaxially arranged at the top of the N well regions; a central N-type region is coaxially arranged above the N-type isolation region; a P well region is arranged above the central N-type region; a P + heavily doped region is coaxially arranged in the P well region; and P-type protection ring regions are symmetrically arrangedon the two sides of the P + heavily doped region. According to the invention, the P well central region, the P-type epitaxial layer central region and the central N-type region are adopted to form anavalanche region, so that the electric field of the avalanche region is reduced, the tunneling effect is inhibited, and the dark counting rate of the device is remarkably reduced.

Single-photon avalanche diode with low dark counting rate and manufacturing method thereof

The invention discloses an SPAD with high detection efficiency and low dark count based on a standard CMOS process. The SPAD is prepared on a P substrate that is provided based on the CMOS process; anN-buried layer is arranged on the P substrate to play an isolation role, the buried N-type injection has the characteristic of inverted doping distribution, the doping concentration increases with the increase of depth, and a virtual protection ring is formed; an N-well region, a P-well region and a heavily doped P+ region are respectively arranged in a diffusion doping region of the N-buried layer, and the N-well region is taken as a component part of a photosensitive PN junction; the P-well region serves as a protection ring; the heavily doped P+ region, a shallow P-well region and the N-type region jointly form a P+P-/N-well photosensitive PN junction, and the combination of two P-type injections with different concentrations form a gradient junction to reduce the dark count of devices; the depletion region of the PN junction is the main occurrence region of avalanche multiplication, and meanwhile, the heavily doped P+ region is also taken as an anode contact region of a photodetector; an N-well contact region is arranged in the N-well region at the edge, and the N-well contact region is a heavily doped N+ region and serves as a cathode contact region of the photodetector.

SPAD with high detection efficiency and low dark count based on standard CMOS process

The invention discloses a broadband high-gain RGC type trans-impedance amplifier with a gate voltage feedback function. The gate of a first MOS transistor and the gate of a second MOS transistor are connected with an input current; the drain of the first MOS transistor and the drain of the second MOS transistor are connected with the gate of a fourth MOS transistor; the source of the first MOS transistor is connected with a power supply; the source of the second MOS transistor is grounded; the source of the fourth MOS transistor and the input current are grounded through a first resistor; thedrain of a third MOS transistor, the drain of the fourth MOS transistor and the gate of a fifth MOS transistor are connected to a voltage output end through a fifth resistor; the gate of the third MOStransistor is grounded, and the source is connected with a power supply VDD; the sources of the fifth MOS transistor, a sixth MOS transistor and a seventh MOS transistor are grounded; the drain of the fifth MOS transistor is connected with the gate of the sixth MOS transistor, and is further connected with the power supply VDD through a second resistor; the drain of the sixth MOS transistor is connected with the gate of the seventh MOS transistor, and is further connected with the power supply VDD through a third resistor; and the drain of the seventh MOS transistor forms the voltage output end VOUT, and is further connected with the power supply VDD through a fourth resistor.

Broadband high-gain RGC type trans-impedance amplifier with gate voltage feedback function

The invention discloses a high-precision multi-channel time-to-digital converter (TDC) The time-to-digital converter adopts a two-stage structure; the first-stage structure adopts a pulse counting type time-to-digital converter based on a carry lookahead adder, and is used for achieving a high working frequency and a wide dynamic range; and the second-stage structure adopts a multi-channel time-to-digital converter based on a voltage-controlled differential time delay unit and a true single phase clocked trigger, and the second-stage structure is used for improving the measurement precision and reducing the measurement error According to the product, the principle of two-stage measurement is utilized, so that the dynamic range and the resolution ratio are taken into consideration A voltage-controlled differential phase inverter and the true single phase clocked (TSPC) trigger are used in the second-stage TDC, so that good linearity and low error rate of a system are ensured; and meanwhile, an integral framework adopts a three-channel structure, so that the length of a single time delay chain is reduced by 2/3, the uncertainty is reduced by 43%, and the performance of the systemis effectively improved

Xie Sheng

Papers

SPAD with high detection efficiency and low dark count based on standard CMOS process

Broadband high-gain RGC type trans-impedance amplifier with gate voltage feedback function

High-precision multi-channel time-to-digital converter