Abstract Approximate computing has become an emerging research topic for energy-efficient design of circuits and systems. Many approximate arithmetic circuits have been proposed, therefore it is critical to summarize the available approximation techniques to improve performance and energy efficiency at a acceptable accuracy loss. This paper presents an overview of circuit-level techniques used for approximate arithmetic. This paper provides a detailed review of circuit-level approximation techniques for the arithmetic data path. Its focus is on identifying critical circuit-level approximation techniques that apply to computational units and blocks. Approximate adders, multipliers, dividers, and squarer are introduced and classified according to their approximation methods. FFT and MAC are discussed as computational blocks that employ an approximate algorithm for implementation.

A survey of approximate arithmetic circuits and blocks

Near-threshold voltage (NTV) operation has the potential to improve the energy efficiency of digital integrated circuits. However, the use of a conservative timing guard band to avoid the timing errors introduces excessive timing margins, thus causing larger energy dissipation in the NTV region. An error-tolerant design based on timing error detection and correction circuits has been shown to be a promising solution to mitigate these issues. This paper presents a light-weight timing error-tolerant flip-flop (ETFF) design. This design detects timing errors using a node transition signal detector with only nine transistors and corrects these errors during the same clock cycle. Moreover, transistor sizing is explored to optimize the trade-off between performance and area overhead. The proposed ETFFs are inserted into a monitored circuit by replacing original flip-flops at timing-monitored points. To further reduce the overhead, we develop a mean-time-to-failure-aware method to select the monitored points by simultaneously considering the critical path coverage and activation rates of flip-flops. The simulation results show that a CNN accelerator using the proposed timing error-tolerant design implemented in the SMIC CMOS 40 nm process can robustly work at 1.1–0.3 V with only 3.5% area overhead. Furthermore, this design reduces the area overhead by 54.68% and improves the energy efficiency by 53.69% at 0.6 V, compared with the Razor flip-flop design. The advantage of the proposed design lies in that it requires smaller circuit overheads and can work reliably in a wider range of supply voltages.

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Design of Light-Weight Timing Error Detection and Correction Circuits for Energy-Efficient Near-Threshold Voltage Operation

Monitoring electrocardiogram signals are of great significance for the diagnosis of arrhythmias. In recent years, deep learning and convolutional neural networks have been widely used in the classification of cardiac arrhythmias. However, the existing neural network applied to ECG signal detection usually requires a lot of computing resources, which is not friendly to resource-constrained equipment, and it is difficult to realize real-time monitoring. In this paper, a binarized convolutional neural network suitable for ECG monitoring is proposed, which is hardware-friendly and more suitable for use in resource-constrained wearable devices. Targeting the MIT-BIH arrhythmia database, the classifier based on this network reached an accuracy of 95.67% in the five-class test. Compared with the proposed baseline full-precision network with an accuracy of 96.45%, it is only 0.78% lower. Importantly, it achieves 12.65 times the computing speedup, 24.8 times the storage compression ratio, and only requires a quarter of the memory overhead.

Arrhythmia Classifier using Binarized Convolutional Neural Network for Resource-Constrained Devices

Cardiac arrhythmia is a medical term to describe an irregular heartbeat, which occurs when electrical properties in the heart incapacitated. Although most of arrhythmias are harmless, some of them can lead to life threatening complications if not detected and monitored on time. To date, a real-time automatic arrhythmia detection is essential in the current health system. This can be seen from numerous research that has been conducted on the automatic detection and classification of various types of arrhythmias. This study seeks to find as much relevant research on the abundance of published work in the topic, to identify the state-of-the art methods and finding the gap in the research in an effort to summarize all of the available evidence of the distinguish real-time automatic arrhythmia detection. A careful quantitative research process of systematic literature review (SLR) within the Health Informatics area was applied in this research to identify and analyze the trends, datasets, and methods in real-time arrhythmia detection. Systematic searches were administered in Scopus using a defined search string, while several filters were applied based on inclusion and exclusion criteria. After removing duplicates and non-eligible articles, the data were extracted from the selected articles with the result shows that the number of studies focusing on the real-time detection of arrhythmia is still limited, but on a rising trend. Finally, the analysis of the datasets, feature extraction, classification methods and a table of algorithm comparison were presented as the result of the study, which summarized the pre-eminent methods of real-time arrhythmia classification based on its average accuracy.

Exploration of ECG-Based Real-Time Arrhythmia Detection: A Systematic Literature Review

Low-voltage computing effectively saves energy in circuit operations, but it suffers from an increasing propagation delay. Approximate computing can significantly reduce the propagation delay by using a simplified or improved circuit, albeit with an inevitable accuracy loss. To address these challenges, a timing-aware configurable adder (TACA) is proposed to achieve a good trade-off between energy efficiency and accuracy at low operating voltages. This design relies on the functions of timing-error detection and correction (TEDC) for the newly-proposed accuracy-configurable full adders (ACFAs). The ACFA operates in an exact mode and two approximate modes by using four transistors as power gating. The TEDC generates timing-error signals when the delay violates the timing constraint due to voltage overscaling. Then, an improved configuration scheme is developed to enable the ACFA to work in an approximate mode by allowing for error signals at runtime. This approximation shortens the carry propagation chain. Thus, the TACA is adapted to timing conditions at different supply voltages by reducing the propagation delay rather than the operation frequency. 

A Timing-Aware Configurable Adder Based on Timing Detection for Low-Voltage Computing

An arrhythmia diagnosis neural network can perform real-time diagnosis through continuous monitoring, and it can warn against potential risks. Moreover, these networks can be installed in resources-constrained devices like wearable devices. However, the existing neural networks suffer from high memory consumption and power consumption, which limit their application in low-power resources-constrained devices. Here, we proposed a novel neural network classifier to classify 17 different rhythm classes using 1,000 long-duration electrocardiograms, achieving a classification accuracy of 95.72%, which is 4.32% higher than current state-of-the-art methods. Additionally, we proposed a layer-wise quantization method based on the greedy algorithm and compared it to other quantization methods. The proposed classifier achieved a 95.39% classification accuracy and reduced memory consumption by 15.5 times. Our study realizes a neural network with high performance and low resources consumption, and it demonstrates the possibility of implementing neural networks in resources-constrained devices for continuous monitoring, real-time diagnosis, and potential risk warnings.

Arrhythmia Classifier Using a Layer-wise Quantized Convolutional Neural Network for Resource-Constrained Devices

Approximate calculation is extensively used in fault-tolerant applications as an extremely effective method of saving energy by balancing performance between accuracy and power consumption. Herein, an adaptive error compensation approximate multiplication and accumulation (AL-MAC) based on the logarithmic principle is proposed, which takes two factors into account. (a) LFC (leftmost-one filtering circuit) extracts the valid bits of the input data for calculation, thus reducing the circuit power consumption and area caused by unnecessary level flipping; (b) ACC (adaptive compensation circuit) conducts the adaptive error compensation, which is compensated according to the error distribution regulation. The evaluation results show that the proposed AL-MAC can save 33.8% of the power consumption and 19.38% of the area in a processing element of the neural network hardware accelerator compared with the standard exact MAC. Moreover, it has good performance on image processing.

AL-MAC: Adaptive Error Compensation Approximate MAC

Approximate computing is extensively used in fault-tolerant applications as an efficient technique of energy saving. To meet the demand of dynamic trade-off between accuracy loss and power saving, more and more configurable approximate architectures have been proposed. However, most of these designs have to introduce large power and area overheads due to the complex circuits for the mode configuration. In this paper, we present a Light-weight Configurable Approximate Adder (LCAA) based on the traditional accurate mirror adder with only 2 extra transistors. This more efficient design can dynamically switch between the accurate and approximate mode at runtime with better tradeoff of the power and accuracy, owing to our proposed novel approximation strategy of the calculation. The simulation results show that compared with the traditional Ripple Carry Adder (RCA), the proposed 16 bits LCAA-based RCA provides up to 43.61% energy savings and 85.01% shorter critical path delay, at the cost of up to 11.96% accuracy degradation in the approximate mode, with only 1.88% more power consumption in the accurate mode. Furthermore, the advantages of our designs are confirmed by the real image addition application.

An Efficient Light-weight Configurable Approximate Adder Design

Near-threshold voltage (NTV) operation has potential to substantially improve the energy efficiency of digital integrated circuits (ICs). However, it also introduces excessive conservative timing margins. The timing resilient circuit was proved to be a promising solution to mitigate excessive timing margins. To realize more energy-efficient IC systems, the timing resilient circuits should be designed to be miniaturized and operate in wide-voltage-range (down to NTV).This paper develops a lightweight timing resilient scheme to enable the near-threshold efficient ICs. The proposed scheme based on our node transition signal detector (NTSD) design with merely 9 extra transistors. Combined with the data strobe Flip-Flops, the circuits are inserted into monitored points of the target ICs. To further reduce the overhead, we develop the mean-time-to-failure aware hybrid selection algorithm. Simulation results demonstrate that the proposed scheme enable the 40-nm CNN accelerator to work robustly at 0.38-1.1V with only 3.5% extra area overhead. Moreover, this scheme reduce area overhead by 54.68% and improve energy efficiency by 53.69% at 0.6V, compared with the presented Razor scheme. The advantage of our proposed method lies in that it consumes less extra overhead and can work stably in a wider voltage range.

Xuemei Fan

Papers

Arrhythmia Classifier Using a Layer-wise Quantized Convolutional Neural Network for Resource-Constrained Devices

Design of Light-Weight Timing Error Detection and Correction Circuits for Energy-Efficient Near-Threshold Voltage Operation

AL-MAC: Adaptive Error Compensation Approximate MAC

An Efficient Light-weight Configurable Approximate Adder Design

A Light-Weight Timing Resilient Scheme for Near-Threshold Efficient Digital ICs