Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with physical model involving the breaking of the ≡ Si s H bonds. The device lifetime τ is proportional to I_{sub}^{-2.9}I_{d}^{1.9}\Delta V_{t}^{1.5} . If I sub is large because of small L or large V d , etc., τ will be small. I sub (and possibly light emission) is thus a powerful predictor of τ. The proportionality constant has been found to vary by a factor of 100 for different technologies, offering hope for substantially better reliability through future improvements in dielectric /interface technologies. A simple physical model can relate the channel field E m to all the device parameters and bias voltages. Its use in interpreting and guiding hot-electron scaling are described. LDD structures can reduce E m and I sub and, when properly designed, reduce device degradation.

Hot-electron-induced MOSFET degradation&#8212;Model, monitor, and improvement

Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with a physical model involving the breaking of the = Si/sub s/H bonds. The device lifetime /spl tau/ is proportional to...

Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement

Short-channel effects in thin-film silicon-on-insulator (SOI) MOSFETs are shown to be unique because of dependences on film thickness and body and back-gate (substrate) biases. These dependences enable control of threshold-voltage reduction, channel-charge enhancement due to a drain bias, carrier velocity saturation, channel-length modulation and its effect on output conductance, as well as device degradation due to hot carriers in short-channel SOI MOSFETs. A short-channel effect exclusive to SOI MOSFETs, back-surface charge modulation, is described. Because of the short-channel effects, the use of SOI MOSFETs in VLSI circuits provides the designer with additional flexibility as compared to bulk-MOSFET design. Various design tradeoffs are discussed. >

Short-channel effects in SOI MOSFETs

A model is developed for an IGFET operating in saturation and accounting for the two-dimensional potential distribution in the section of the surface space-charge region adjacent to the drain. This section is treated as a volume obeying Gauss's law, thereby enabling the charge contained in it to be related to the integral of the electric displacement density normal to its surface without the need to consider the detailed distribution of charge inside. The resulting model shows, explicitly, the dependence of device output characteristics on applied potentials, geometric and processing parameters. It is also shown that by making adequate approximations, simple yet accurate forms of the model are obtained. The accuracy of the model is demonstrated by comparisons between calculated and measured device output characteristics.

A simple two-dimensional model for IGFET operation in the saturation region

A charge-based large-signal transient model for the enhancement-mode thin-film SOI MOSFET in strong inversion, suitable for circuit simulators such as SPICE, is presented. The model physically accounts for the predominant short-channel effects in MOSFET's (namely threshold-voltage reduction, drain-induced conductivity enhancement, velocity saturation with mobility degradation, and channel-length modulation) as influenced by the unique features of thin SOI devices (i.e. the presence of an additional back gate and the possibility of a floating film body). It includes a description of generation current due to (weak) impact ionization, which can have a far greater influence on SOI (as compared to bulk) MOSFET's due to the associated charging of the floating body. Measurements on devices of varied geometry show good agreement with model predictions. The model is implemented in SPICE2, to be used for circuit and device CAD, and TECAP, for automated parameter extraction. >

A physical short-channel model for the thin-film SOI MOSFET applicable to device and circuit CAD

A model is developed for the substrate current of an IGET operating in saturation. This current results from the impact ionization of the channel current carriers in the high field region adjacent to the drain. Due to the exponential dependency of the impact ionization process on the electric field, an accurate description of the field near the drain is essential. An expression for the field, accounting for the two-dimensional nature of the drain space charge region, is used. The result is a closed form expression for the substrate current. By using an appropriate p-n junction model for the source diffusion, the floating substrate potential in SOS devices is evaluated.

Modelling weak avalanche multiplication currents in IGFETS and SOS transistors for CAD

Using simple charge-voltage relationships, a four terminal model is developed for the depletion-mode IGFET. Various conditions, which can co-exist at the surface such as accumulation, depletion and inversion, are taken into account. The basic model elements, namely the source-drain transport current and the various charging currents, are explicitly given in terms of known processing data. Device parameters essential to device design such as threshold voltage, drain saturation voltage and conditions for surface inversion are directly related to implanted layer characteristics.

A nonlinear CAD model for the depletion-mode IGFET

As presented above, the IGFET model does not include channel-shortening effects; L is a constant channel length. The modelling of these effects is treated specifically in Paper 3.2, the results of which, in association with the present model, give a complete representation of the device. For comparison between the model and measured device characteristics, devices should here be chosen with sufficiently long channels for channel-shortening effects to be negligible in this respect.

A new accurate model of the IGFET for CAD applications

The characteristics of an IGFET operating in saturation are developed in terms of an approximate two-dimensional model of the drain section of the space charge region. This section is treated as a volume obeying Gauss's law, thereby enabling the charge contained in it to be related to the integral of the electric displacement density normal to its surface without having to consider the detailed distribution of charge inside. An explicit expression is obtained for the drain conductance showing its dependence on device geometry, processing parameters and applied voltages. Closed form solutions for the current and conductance are obtained by neglecting the mobile carriers in the drain section. Substrate currents are evaluated using a simple impact ionization model.

Y.A. El-Mansy

Papers

Modelling weak avalanche multiplication currents in IGFETS and SOS transistors for CAD

A nonlinear CAD model for the depletion-mode IGFET

A new accurate model of the IGFET for CAD applications

A simple two-dimensional saturation model of short-channel IGFETS for CAD applications