The current status of VLSI layout and directions for future research are addressed, with emphasis on the authors' own work Necessary terminology and definitions and, whenever possible, a precise formulation of the problems are provided Placement and floorplanning for both the sea-of-gates and building-block designs are examined The former emphasizes the connectivity specification, whereas the latter must also consider module shape and size Global routing based on a method of successive cuts on a chip is discussed This is a hierarchical top-down approach that is useful for both of the above designs A two-dimensional detailed routing problem and the rip-up and rerouting problem are also discussed The field of computational geometry and its application to layout-in particular, to gridless routing and compaction-are reviewed, and layout engines are considered >

Recent advances in VLSI layout

Symbolic layout and compaction is reaching a mature status. This is demonstrated, in part, by the recent or imminent introductions of a number of commercial symbolic layout and compaction systems. The two most frequently used symbolic layout compaction approaches, constraint graph compaction and virtual grid compaction, are reviewed in this paper. The current status of these two approaches is presented by looking at the results of the ICCD87 compaction benchmark session.

Symbolic layout compaction review

A new technique for 2-dimensional layout compaction of integrated circuits is presented. After a traditional one-dimensional precompaction step, the size of the layout is further reduced with a technique that bears a strong similarity to the technique of 'zone-refining' used in the purification of crystal ingots. Individual circuit components or small clusters of components are peeled off row by row from the precompacted layout, moved across an open zone, and reassembled at the other end of this zone in a denser configuration. In this process both coordinates of the moved components are altered and jogs are introduced in the connecting wires between them to produce the needed flexibility for placing components into optimal positions. The constraint graphs in both the x- and y-direction are used and updated concurrently.

Two-Dimensional Compaction by 'Zone Refining'

The Siemens RTL tiled window manager automatically adjusts the size and position of tiled windows to balance competing demands for screen space. The degree of automation can be set by both the user and control strategies, which range from strictly local to those which can affect all the windows on the screen. These strategies are discussed, the trade-offs involved are indicated and the algorithms used in their implementation are briefly described. >

Automatic strategies in the Siemens RTL tiled window manager

This paper presents a graph-theoretic compactor that minimizes the areas of the bounding rectangle and the individual rectangles in the layout. The minimization problem is formulated as a two-stage process. In the first stage, the area of the bounding rectangle is minimized, and in the second stage, the weighted sum of the areas of the individual rectangles is minimized, which automatically minimizes the lengths of the inter-connecting wires. This approach provides a general and rigorous method for wire-length minimization. Algorithms for generating and solving the constraint graph are proposed. The minimization algorithm includes a graph-theoretic Simplex method that can be used to solve minimization problems whose constraints can be expressed in terms of a directed graph.

Minplex - A Compactor that Minimizes the Bounding Rectangle and Individual Rectangles in a Layout

Compaction is the CAD tool used to pack rough sketches or symbolic diagrams to produce IC layouts. Manual compaction is tedious, time-consuming, and error-prone; automated compaction tools can greatly shorten the layout design cycle. This paper reviews the historical background and the major developments in the field of compaction, emphasizing subjective evaluations rather than objective descriptions. The major approaches covered are constraint-graph, shear-line, and virtual-grid. Various ideas for further reducing chip area (such as inserting jog points, shortening wires, dense packing, 2-D compaction, and interactive tools) are also discussed. Because of the critical role of efficient algorithms in VLSI CAD systems, analyses of computational complexities are also included.

Y.E. Cho

Papers

A Subjective Review of Compaction