A wide dynamic range CMOS image sensor with a burst readout multiple exposure method is proposed. In this method, maximally four different exposure-time signals are read out in one frame. To achieve the high-speed readout, a compact cyclic analog-to-digital converter (ADC) with noise canceling function is proposed and arrays of the cyclic ADCs are integrated at the column. A prototype wide dynamic range CMOS image sensor has been developed with 0.25-/spl mu/m 1-poly 4-metal CMOS image sensor technology. The dynamic range is expanded maximally by a factor of 1791 compared to the case of single exposure. The dynamic range is measured to be 19.8 bit or 119 dB. The 12-bit ADC integrated at the column of the CMOS image sensor has DNL of +0.2/-0.8 LSB.

A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters

This paper presents a CMOS imager with a column-parallel ADC architecture based on a multiple-ramp single-slope (MRSS) ADC. Like the well-known column-level single-slope ADC, an MRSS ADC uses a very simple analog column circuit, which mainly consists of an analog comparator and some switches. A prototype imager using the MRSS ADC architecture was realized in a 0.25 CMOS process. Measurements demonstrate that the conversion speed of an MRSS ADC is 3.3 higher than a single-slope ADC while dissipating only 16% more power. Furthermore, the MRSS ADC can be easily adapted to exhibit a companding characteristic, which exploits the amplitude-dependent nature of the photon shot noise present in imager signals. Measurements show that the resulting multiple-ramp multiple-slope ADC is 25% faster than an MRSS ADC while dissipating the same amount of power.

Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors

Analysis of dynamic-range (DR) and signal-to-noise-ratio (SNR) for high fidelity, high-dynamic-range (HDR) image sensor architectures is presented. Four architectures are considered: (i) time-to-saturation, (ii) multiple-capture, (iii) asynchronous self-reset with multiple capture, and (iv) synchronous self-reset with residue readout. The analysis takes into account circuit nonidealities such as quantization noise and the effects of limited pixel area on building block and reference signal performance and accuracy. Examples that demonstrate the behavior of SNR in the extended DR and implementation and power consumption issues for each scheme are presented.

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Quantitative study of high-dynamic-range image sensor architectures

Accurate modeling of image noise is important in understanding the relative contributions of multiple-noise mechanisms in the sensing, readout, and reconstruction phases of image formation. There is a lack of high-level image-sensor system modeling tools that enable engineers to see realistic visual effects of noise and change-specific design or process parameters to quickly see the resulting effects on image quality. This paper reports a comprehensive tool, written in MATLAB, for modeling noise in CMOS image sensors and showing the effect in images. The tool uses accepted theoretical/empirical noise models with parameters from measured process-data distributions. Output images from the tool are used to demonstrate the effectiveness of this approach in determining the effects of various noise sources on image quality

A Comprehensive Tool for Modeling CMOS Image-Sensor-Noise Performance

A CMOS image sensor that can operate in both linear and logarithmic mode is described. Two sets of data are acquired and combined in the readout path to render a high dynamic range image. This is accomplished in real-time without the use of frame memory. A dynamic range in excess of 120 dB was achieved at 26 frames/s (352times288-array). The system addresses the problems of high fixed pattern noise (FPN), slow response time, and low signal-to-noise ratio (SNR) in logarithmic mode. FPN has been effectively reduced by single and two parameter calibration, the latter achieving FPN of 2% per decade. A novel on-chip method of deriving a reference point has been implemented. The system is fabricated in a 0.18-mum 1P4M process and achieves a pixel pitch of 5.6 mum with 7 transistors per pixel

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Extended Dynamic Range From a Combined Linear-Logarithmic CMOS Image Sensor

A 30 frames/s SXGA 5.6 /spl mu/m pinned photodiode pixel column parallel CMOS image sensor achieves 340 /spl mu/V noise floor and 40 pA/cm/sup 2/ dark current. Performance is limited by pixel 1/f noise, not by the ADC noise floor of 140 /spl mu/V. The column ADC memory employs a custom DRAM to save area. The sensor utilizes a 0.35 /spl mu/m 1P 3M CMOS process.

Y. Marcellier

Papers

SXGA pinned photodiode CMOS image sensor in 0.35 /spl mu/m technology