This paper describes large-scale-integration programmable processors designed for multimedia processing such as real-time compression and decompression of audio and video as well as the generation of computer graphics. As the target of these processors is to handle audio and video in real time, the processing capability must be increased tenfold compared to that of conventional microprocessors, which were designed to handle mainly texts, figures, tables, and photographs. To clarify the advantages of a high-speed multimedia processing capability, we define these chips as multimedia processors. General-purpose microprocessors for workstations and personal computers (PCs) use special built-in hardware for multimedia processing, so the multimedia processors described include these modified general-purpose microprocessors. After reviewing the history of programmable processors, we classify multimedia processors into five categories depending on their basic architecture. The categories are reduced instruction set computer (RISC) microprocessors for workstations, complex instruction set computer microprocessors for PCs, embedded RISCs, low-power digital signal processors (DSPs), which are mainly used for mobile communications devices, and media processors that support PCs for multimedia applications. These five classes are then grouped into two: microprocessors with a multimedia instruction set and highly parallel DSPs. An architectural comparison between these two groups on the basis of Moving Picture Experts Group decoding applications is made, and the advantages and disadvantages of each class are clarified. Future processors, including "system on a chip," and their applications are also discussed.

http://ieeexplore.ieee.org/iel5/5/15068/00687835.pdf

Multimedia processors

To reduce the amount of computations for a full search (FS) algorithm for fast motion estimation, we propose a new and fast FS motion estimation algorithm. The computational reduction of our FS motion estimation algorithm comes from fast elimination of impossible motion vectors. We obtain faster elimination of inappropriate motion vectors using efficient matching units from localization of a complex area in image data. In this paper, we show three properties in block matching of motion estimation. We suggest two fast matching scan algorithms: one from adaptive matching scan and the other from fixed dithering order. Experimentally, we remove the unnecessary computations by about 30% with our proposed algorithm compared with the conventional fast FS algorithms.

Fast full search motion estimation algorithm using early detection of impossible candidate vectors

Metabolic syndrome (MetS) is a combination of disorders that increase one's risk for type 2 diabetes (DM2) and cardiovascular disease (CVD). Both lifestyle and genetic factors have been established to be involved in the aetiology of MetS. Improving our knowledge about the pathophysiology of MetS could provide more effective therapeutic approaches and reduce the risk of developing DM2 and CVD. Lower levels of adiponectin, an adipose-derived protein, has been shown to be associated with the components of MetS. Common variants in a number of candidate genes related to MetS have been shown to be associated with changes in the serum adiponectin level. This study was designed to evaluate the putative effects of military lifestyle, as well as common polymorphisms of the peroxisome proliferator activated receptor gamma 2 (PPARγ2), insulin receptor substrate-1 (IRS-1) and adiponectin (APM1) genes on serum adiponectin level in a cohort of Finnish servicemen. Results of this study have showed that serum adiponectin significantly decreased during the sixmonth follow up in military service compared to baseline levels. This decrease was even shown in subjects that experienced a 5-10 % weight loss after six-months. Subjects with the Ala12Ala genotype of PPARγ2 had significantly higher levels of serum adiponectin compared with subjects with the Pro12Ala and Pro12Pro genotypes. Subjects having the X12Ala genotype of PPARγ2 with > 10% weight reduction showed a significant increase in serum adiponectin compared to other groups during the follow up. Those having the Ala12Ala genotype of PPARγ2 + Gly972Gly genotype of IRS-1 combination had significantly higher adiponectin compared with subjects with the Pro12Pro + Gly972Gly and Pro12Ala + Gly972Gly genotype combinations. Adiponectin levels were significantly higher in men with the T276T genotype compared with subjects with the G276T or G276G genotypes of SNP+276 of the APM1 gene. In conclusion, this study shows a possible impact of a military lifestyle as well as, candidate gene variations, and their interactions upon the regulation of serum adiponectin levels as a marker of MetS. This study could serve as a pilot for the further extensive studies with longer follow up periods as well as more accurate information on specific lifestyle factors.

A b c d e f g ...

A full-search based block-matching algorithm for motion estimation has a major problem of significant computational load. To solve this problem, extensive research in fast-motion estimation algorithms have been carried out. However, most of them have some degradation in the predicted image from the reduced computation. To decrease the amount of significant computation of the full-search algorithm, we propose a fast block-matching algorithm based on an adaptive matching scan and representative pixels without any degradation of the predicted image. By using Taylor series expansion, we obtain the representative pixels and show that the block-matching errors from the reference block and candidate blocks are proportional to the block complexity. With the derived result, we propose a fast full-search algorithm with adaptive scan direction in block matching. Experimentally, our proposed algorithm is very efficient in terms of computational speedup, and is the fastest among all the conventional full-search algorithms. Therefore, our algorithm is useful in VLSI implementation of video encoders for real-time encoding.

A fast full-search motion-estimation algorithm using representative pixels and adaptive matching scan

We have developed a new digital signal processor (DSP) core for handheld terminals, the SPXK5 performance and flexibility, is compatible with high-level languages, and its architecture features low-power consumption. We describe the SPXK5 architecture and its performance in DSP applications. We also consider the question of application-specific enhancements. Such architecture enhancements as add-compare-select instructions or coprocessors for the Viterbi (1995) decoding algorithm are employed in some programmable DSPs, and for video codecs, other architectures include either single-instruction multiple-data (SIMD) instructions or media coprocessors. While such application-specific enhancements are valuable when their applications are actually in use, they do nothing to enhance the performance of other applications, and the more they are added, the greater the increase in chip size and energy requirements. In other words, for handheld terminals, such enhancements need to be chosen in a careful and balanced way. We have done this in developing the SPXK5, in which a wide range of signal processing algorithms are efficiently implemented.

VLIW DSP for mobile applications

Motion estimation (ME) has widely been used in video codecs, such as MPEG and ITU-T H.261, to remove interframe redundancy. This paper describes a fast full-search ME method for programmable processors with a multiply-accumulator. It is based on the block matching method that evaluates block mismatch by the mean square error. In order to reduce the computational load of the ME, a fast two-dimensional FIR filtering algorithm is applied, and the redundancy of the overlapped area computation among the reference blocks is eliminated. When the block size is 16/spl times/16 and the number of reference blocks in the search window is 32/spl times/32, this method reduces the computational load to 22.6% without degrading the motion tracking capability.

A fast full-search motion estimation method for programmable processors with a multiply-accumulator

This paper describes an H.263 video codec implementation based on a low power consumption general purpose DSP. Fast algorithms, such as a fast motion estimation algorithm and a low complexity noise reduction filter, are proposed to implement the video codec on a single DSP chip maintaining sufficient picture quality. By using a 50 MIPS, 100 mW DSP, the developed codec encodes and decodes 7.5 QCIF frames per second, which is sufficient performance for low bit-rate video compression, typically below 64 kbps.

Y. Naito

Papers

A fast full-search motion estimation method for programmable processors with a multiply-accumulator

H.263 mobile video codec based on a low power consumption digital signal processor