A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m CMOS technology. It requires 8500 mil/SUP 2/, consumes 180 mW, and has an input capacitance of 3 pF. A fully differential architecture is used; only a two-phase nonoverlapping clock is required, and an on-chip sample-and-hold amplifier is included.

https://www.ee.columbia.edu/~kinget/EE6312_S04/project/refs/lewis_pipelined_ad_jssc_dec_1987.pdf

A pipelined 5-Msample/s 9-bit analog-to-digital converter

The authors describe the design of a VLSI-compatible CMOS comparator for high-speed applications. An examination of various generic approaches to obtaining the nonlinear amplification needed to perform the function of comparison leads to the conclusion that this amplification can best be obtained by means of regeneration. Based on this conclusion, a CMOS comparator has been designed wherein voltage comparisons are accomplished directly by a pipelined cascade of two regenerative sense amplifiers, without the use of a preamplifier. To ensure an input resolution of at least 8-bits, offset cancellation is incorporated in the first sense amplifier. The comparator has been integrated in a 2- mu m CMOS technology and has a maximum sampling rate of over 100 MHz; it operates from a single +5-V supply and dissipates only 3.6 mW at its maximum sampling rate. >

A 100-MHz pipelined CMOS comparator

In the comparator circuit, the amplifier circuit (6) is comprised of an inverting amplifier section (21) having a high gain and a noninverting amplifier section (22) having a low output impedance. Therefore, the comparator circuit has a high input sensitivity. The comparator circuit also can operate at a high speed.

Voltage comparator circuit

THE IMPORTANCE O F CMOS flash A/D converter^"^'^ with superior cost-effectiveness and VLSI logic compatibility has increasingly been recognized for such applications as high-speed data acquisition and digital video-signal processing. However, they demand both a high conversion rate of above 20MIlz and a high-resolution of more than 8b; which have only recently been achieved with CMOS technology. This has been due to the lack of CMOS comparators suitable for use in this flash converter, which requires not only more stringent device-ratio matching for higher-resolution, but also high-speed and highdensity. This paper will cover a monolithic CMOS 8 b video-speed flash A/D converter using a high-speed offset-reduction comparator technique, which has experimentally shown the capability of a high-resolution of up to 9b and above at high videospeed. The converter was implemented by standard 2 p silicongate CMOS technology including only one capacitor process (AI-poly Si).

CMOS 8b 25MHz flash ADC

An A/D converter comprises a resistor ladder connected between first and second reference potentials so that each connection tap provides a different divided reference potential. A plurality of first switches are each connected at their one end to one connection tap of the resistor ladder and at their other end to a corresponding number of common connection nodes. Also, a plurality of second switches are each connected at their one end commonly to an input for an analog voltage signal and at their other end to the corresponding common connection nodes. Each of the nodes is connected through one coupling capacitor to one amplifier having adapted to generate an output signal representative of whether the voltage of the input signal is higher or lower than a voltage appearing at the above mentioned one connection tap of the resistor ladder. Each of the amplifier has a third switch connected between the input and the output of the amplifier, and an encoder is connected to the output of each amplifier so as to generate an digital signal corresponding to the input analog signal. Each of the common connection nodes are connected through an associated fourth switch to a bias voltage source. In a pre-calibration period proceeding to a calibration period, the third and fourth switches are closed so that the respective common connection nodes are forcedly and rapidly charged or discharged through the bias voltage source.

Flash A/D Converter

A 3.5μm bulk CMOS Si-gate process applied to the design of a 20MS/s flash A/D converter powered by a single 5V supply, will be reported. By employing non-sampling amplifiers in a comparator array, 7b accuracy has been achieved with a power dissipation of 150mW.

http://ieeexplore.ieee.org/iel6/8299/25931/01156643.pdf

Y. Sato

Papers

A bulk CMOS 20MS/s 7b flash ADC