A common approach to the over-the-cell channel routing problem is to divide the problem into three steps: (1) routing over the cells; (2) choosing net segments; and (3) routing within the channel. It is shown that the first step can be reduced to the problem and finding a maximum independent set of a circle graph, and thus can be solved optimally in quadratic time. Also, it is shown that to determine an optimal choice of net segments in the second step is NP-hard in general, and an efficient heuristic algorithm for this step is presented. The third step can be carried out using a conventional channel router. On the basis of these theoretical results, an over-the-cell channel router that produces solutions which are better than the optimal two-layer channel routing solutions for all test examples is designed. The over-the-cell channel router also outperforms the over-the-cell channel router described by Y. Shiraishi and Y. Sakemi (ibid., vol.CAD-6, no.3, p.462-71, 1987). In particular, for Deutsch's difficult example, the solution yields a saving of 10.5% in channel routing area when compared with the optimal two-layer channel routing solution, and a saving of 15% in channel routing area when compared with the routing solution produced by the over-the-cell channel router. >

Over-the-cell channel routing

When an over-the-cell routing layer is available for standard cell layout, efficient utilization of routing space over the cells can significantly reduce layout area. In this paper, we present three physical models to utilize the area over the cells for routing in standard cell designs. We also present efficient algorithms to choose and to route a planar subset of nets over the cells so that the resulting channel density is reduced as much as possible. For each of the physical models, we show how to arrange inter-cell routing, over-the-cell routing and power/ground busses to achieve valid routing solutions. Each algorithm exploits the particular arrangement in the corresponding physical model and produces provably good results in polynomial time. We tested our algorithms on several industrial standard cell designs. In our tests, this method reduces total channel density as much as 21%.

General models and algorithms for over-the-cell routing in standard cell design

We propose a new approach for reducing the density of a channel by routing some nets (or subnets) over the cells (i.e., outside the channel). Previous research assumed that the more nets being routed over the cells the greater the reduction in the channel density. We show that only the removal of critical nets contributes to the re- duction in the channel density. We divide channel into zones where each zone has a zone density and the removal of any net from a zone will reduce its density by one. In order to reduce the channel density, only certain critical zones need to have their nets routed over the cells. A bipartite graph is used to represent the relationship between nets and zones. The problem is transformed into a constrained covering problem and formulated as an integer linear programming problem. In comparison with previous research, our approach reduces more channel densities while using fewer tracks over the cells. For Deutsch's difficult khannel, a previous aiiproach needs 15 tracks over the cells to reduce the channel density by 3 while we need only 5 tracks to achieve the same result . Index Terms-Over-the-cell routing, channel density reduction, stan- dard-cell layout, VLSI routing, integer linear programming.

Channel density reduction by routing over the cells

A description is given of a program, Excellerator, which automatically generates full-custom symbolic CMOS cell layouts. The input is a transistor-level netlist with optimal constraints on layout shape and I/O port positions. The output is a high-quality virtual-grid-based layout suitable for use in a two-dimensional tiling methodology. I/O port locations can be optimized. Versatile support for different layout shapes and port locations makes this system ideal for use in a top-down, fully automatic physical design system. Transistor routing is provided by a novel, recursive version of the A-Star search procedure. This technique reduces the frequency and seriousness of routing blockages by finding near-optimal compromises between new connections and reroutes of previous connections. Routing occurs in two metal layers plus polysilicon and diffusion, and is easily extendable to any number of routing layers. Routing priority can be given to critical nodes. >

Excellerator: custom CMOS leaf cell layout generator

We introduce the single-layer global routing problem (SLGRP), also called homotopic routing or rubber-band-equivalent routing, and propose a technique for solving it. Given a set of nets, the proposed technique first determines the routing sequence based on the estimated congestion, the bounding-box length and priority. Then, it finds a routing path, being a sequence of tiles, for each net (one net at a time), avoiding "congested" areas. The overall goal of the algorithm is to maximize the number of routed nets. The proposed global router is the first true single-layer global router ever reported in the literature. The size of tiles, w/spl times/w, is an input parameter in our algorithm. For w=1, the proposed global router serves as an effective detailed router. An optimal postprocessing algorithm, minimizing wire length and number of bends, under homotopic transformation, is presented. The technique has been implemented and tried out for randomly generated data. The algorithm is very efficient and produces good results. >

Single-layer global routing

A permeation routing algorithm is proposed which decides the detailed routes on a new layout model. The permeation router attains a higher density by using the expanded routing region as well as the conventional one simultaneously. This routing algorithm consists of two phases. One is to partition the trunk set into three subsets corresponding to the trunks to be routed in the channel on the lower transistor row, upper transistor row, or between transistor rows. The other is to route these channels by using the one-layer channel assignment method as well as the conventional one. The experiments show that the routing results are practical and that the processing time is proportional to the number of trunks to the power of 1.4.

A Permeation Router

Three kinds of feedthrough assignment algorithm are suggested for CMOS logic cell layout, and their solutions and processing times are compared. One is based on the idea that the feedthrough requirement with fewest feedthrough candidates is first assigned. The second is an optimum algorithm that solves the problem by formalizing it as an integer programming problem. The third is a combination of the two, in which the first algorithm is applied until all of the uniquely determined feedthroughs are assigned, and then the second one is applied. The second and third algorithms attain the optimum solution, but the first one does- not. The deviation of the first algorithm from the optimum solution is shown to be within 3.5% of the optimum. and the cell area increases less than 3.5%. The processing times of the first and third algorithms are 1/27.5 and 1/3.0, respectively, on average, of that of the optimum one. Thus it is concluded that the first algorithm, although not optimum, is practical, and may well be incorporated into the feedthrough assignment process. >

Y. Shiraishi

Papers

A Permeation Router

Optimality of a feedthrough assignment algorithm in a CMOS logic cell layout