An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Power semiconductor devices and methods of manufacture

A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Power semiconductor device

An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.

Compound semiconductor device and method of manufacturing the same

PROBLEM TO BE SOLVED: To increase a withhold voltage of a vertical MOS filed effect transistor 1. SOLUTION: This vertical MOS field effect transistor 1 has a super junction structure 13. The super junction structure 13 is a structure wherein first conductive semiconductor regions and second conductive semiconductor regions are arranged alternately in a direction vertical to a current flow in a drift region. An insulating region 35 is positioned outside a silicon single crystal region (P-type silicon single crystal region 15) located at an end of the super junction structure 13. The insulating region 35 is formed by burying a silicon oxide film in a trench 33. COPYRIGHT: (C)2001,JPO

Vertical semiconductor device

PROBLEM TO BE SOLVED: To suppress the fluctuation of the current sensing ratio of a semiconductor device at an atmospheric temperature. SOLUTION: A semiconductor device forms a main region 1 in which main current flows and a sensing region 2 in which branched current flows on the same substrate, and numbers of cells in the sense cell region 2 amount to not more than 0.1% of the numbers in the main cell region. At that time, a resistant temperature coefficient of a peripheral cell existing along the boundary of the regions is equal to that of an inside cell existing away from the boundary. Otherwise, the ratio of the numbers of the peripheral cell and the inside cell is equal in the main region 1 and the sensing region 2. COPYRIGHT: (C)2005,JPO&NCIPI

Semiconductor device having current sensing function

PROBLEM TO BE SOLVED: To realize a device that satisfies the request of both low on-state resistance and high break down voltage by reducing effectively the current amplifying factor of parasitic bipolar transistors without increasing the on resistance of power MOSFET transistor. SOLUTION: A power device such as a power MOSFET with high avalanche breakdown voltage is realized by burying an oxide film 230 into an element and utilizing an SOI structure positively. The lifetime of the minority carrier of the single crystal of a region 310 around a boundary on an embedded oxide film 230 is shorter than the lifetime of the minority carrier of the single crystals of other regions so that the lifetime of the minority carrier can be made far shorter than that of a general epitaxial Si layer and the hFE of the parasitic bipolar transistors can be made very low value. COPYRIGHT: (C)1997,JPO

Insulated gate semiconductor device and method of manufacture

PROBLEM TO BE SOLVED: To provide a vertical MOS field effect transistor for decreasing on- resistance and at the same time increasing a breakdown voltage. SOLUTION: In a vertical MOS field effect transistor 1, a buried electrode 11 is buried into a trench 21. a selective oxide film 25 that is formed by the selective oxidation method is located on the sidewall of the trench 21b, thus reducing a width W of an n--type drift region 17 that is located between the trenches 21b as compared with a distance D between trenches 21a in an n+-type source region 13. COPYRIGHT: (C)2001,JPO

Vertical semiconductor device and its manufacturing method

PURPOSE: To provide a method of manufacturing a semiconductor memory device (DRAM) more enhanced in degree of integration exceeding a prior art. CONSTITUTION: A stereoscopic SOI(Silicon-On-Insulator) structure is formed on a part of a silicon substrate, and a capacitor and an insulated gate field effect transistor channel forming region are formed in one piece inside the SOI structure. The channel forming region (130a, b) of an insulated-gate field effect transistor is formed on the side wall of the stereoscopic SOI structure, the drain (or source) region of the insulated-gate field effect transistor is formed as continuously connected to the channel forming region, and a capacitor is formed overlapping with the drain (or source) region. COPYRIGHT: (C)1996,JPO

雅人樹神

Papers

Vertical semiconductor device

Semiconductor device having current sensing function

Insulated gate semiconductor device and method of manufacture

Vertical semiconductor device and its manufacturing method

Semiconductor memory device and manufacture thereof

雅人 樹神

Papers

Vertical semiconductor device

Semiconductor device having current sensing function

Insulated gate semiconductor device and method of manufacture

Vertical semiconductor device and its manufacturing method

Semiconductor memory device and manufacture thereof

雅人樹神