Showing papers by "Yaser Jararweh published in 2011"

AES-512: 512-bit Advanced Encryption Standard algorithm design and evaluation

Abstract: This paper presents an FPGA architecture for a new version of the Advanced Encryption Standard (AES) algorithm. The efficient hardware that implements the algorithm is also proposed. The new algorithm (AES-512) uses input block size and key size of 512-bits which makes it more resistant to cryptanalysis with tolerated area increase. AES-512 will be suitable for applications with high security and throughput requirements and with less chip area constrains such as multimedia and satellite communication systems. An FPGA architectural for AES-512 was developed using VHDL, and synthesized using Virtix-6 and Virtex-7 chips. AES-512 show tremendous throughput increase of 230% when compared with the implementation of the original AES-128.

An optimal multi-processor allocation algorithm for high performance GPU accelerators

Abstract: An optimal algorithm for Multi-Processor Allocation in GPU system that reduce power consumption while maintain the application required performance is presented in this paper. Power consumption and heat dissipation have become critical issues in modern high performance computing systems due to the rising cost of electricity and the cooling infrastructure. The Multi-Processor Allocation (MPAlloc) algorithm will determine the appropriate number of Multi-Processor at runtime that can reduce power consumption, resources over-provisioning, and maintain performance simultaneously. It uses the memory BandWidth Utilization (BWU) metric to predict the MultiProcessor requirements of the application. The experimental results showed that a 14.2% of power saving could be achieved using the MPAlloc algorithm with less than 1% of performance degradation.