Showing papers by "Yaser Jararweh published in 2012"

Hardware Performance Evaluation of SHA-3 Candidate Algorithms

Abstract: Secure Hashing Algorithms (SHA) showed a significant importance in today’s information security applications. The National Institute of Standards and Technology (NIST), held a competition of three rounds to replace SHA1 and SHA2 with the new SHA-3, to ensure long term robustness of hash functions. In this paper, we present a comprehensive hardware evaluation for the final round SHA-3 candidates. The main goal of providing the hardware evaluation is to: find the best algorithm among them that will satisfy the new hashing algorithm standards defined by the NIST. This is based on a comparison made between each of the finalists in terms of security level, throughput, clock frequancey, area, power consumption, and the cost. We expect that the achived results of the comparisons will contribute in choosing the next hashing algorithm (SHA-3) that will support the security requirements of applications in todays ubiquitous and pervasive information infrastructure.

An Integrated Radix-4 Modular Divider/Multiplier Hardware Architecture for Cryptographic Applications

Abstract: The increasing importance of security in computers and communication systems introduces the need for several public$key cryptosystems. The modular division and multiplication arithmetic operations in GF (p) and GF (2 n ) are extensively used in many public key cryptosystems, such as El$Gamal cryptosystem, Elliptic Curve Cryp tography (ECC), and the Elliptic Curve Digital Signature Algorithm (ECDSA). Processing these cryptosystems involves complicated computations, therefore, it is recommended to develop specialized hardware to speed up these computations. In this work, we propose efficient hardware design to compute both operations (division and multiplication) in the binary extension finite filed (GF (2 n ). The common points in both operations are utilized in our design to reduce the design area and delay. making the proposed architecture faster than other previously proposed designs. The FPGA implementation of the proposed design shows better results compared with other designs in this field.

Power and Performance Management of GPUs Based Cluster

Abstract: Power consumption in GPUs based cluster became the major obstacle in the adoption of high productivity GPU accelerators in the high performance computing industry. The power consumed by GPU chips represent about 75% of the total GPU based cluster power consumption. This is due to the fact that the GPU cards are often configured at peak performance, and consequently, they will be active all the time. In this paper, the authors present a holistic power and performance management framework that reduces power consumption of the GPU based cluster and maintains the system performance within an acceptable predefined threshold. The framework dynamically scales the GPU cluster to adapt to the variation of incoming workload's requirements and increase the idleness of the of GPU devices, allowing them to transition to low-power state. The proposed power and performance management framework in GPU cluster demonstrated 46.3% power savings for GPU workload while maintaining the cluster performance. The overhead of the proposed framework is insignificant on the normal application\system operations and services.

Exploiting GPUs for compute-intensive medical applications

Abstract: Medical applications are compute and data intensive applications. The complex mathematical models and differential equations in the medical domain require huge computations. Cardiac simulation is one example of such compute-intensive application. In this work, we present an evaluation study for porting the cardiac simulator to the high performance GPUs accelerators. We also conducted a comparative evaluation for using conventional computing platforms: a single CPU and a CPU Cluster system. Our study shows that tremendous speed-up gain can be achieved using GPU-based system over cluster-based system or single CPU systems.