A data storage device is disclosed comprising a non-volatile memory comprising a plurality of memory segments. When a write command comprising a logical block address (LBA) is received, a number of consecutive memory segments to access in response to the write command is determined. When the number of consecutive memory segments to access is greater than a threshold, a new run-length mapping entry in a run-length mapping table (RLMT) is created. When the number of memory segments to access is not greater than a threshold, at least one new single address mapping entry in a single address mapping table (SAMT) is created.

Data storage device employing a run-length mapping table and a single address mapping table

A disk drive is disclosed comprising a head actuated over a disk having a plurality of tracks, wherein each track comprises a plurality of data sectors each assigned a physical block address (PBA). A first write command is received identifying a number of logical block addresses (LBAs) and write data. A header identifier is written to a first data sector that identifies a beginning of the first write command. The write data is written to a plurality of the data sectors and after writing the write data, a footer identifier is written to a second data sector that identifies the end of the first write command. The LBAs are written to at least one of the first data sector and the second data sector.

Disk drive framing write data with in-line mapping data during write operations

A non-volatile storage system is provided with reduced delays associated with loading and updating a logical-to-physical mapping table from non-volatile memory. The mapping table is stored in a plurality of segments, so that each segment can be loaded individually. The segmented mapping table allows memory access to logical addresses associated with the loaded segment when the segment is loaded, rather than delaying accesses until the entire mapping table is loaded. When loading mapping segments, segments can be loaded according to whether there is a pending command or by an order according to various algorithms.

Solid-state drive with reduced power up time

Systems and methods for writing a sequence of data to a disk drive using sorted data zones are provided. One embodiment includes a disk drive comprising one or more disks having a plurality of disk surfaces, wherein each disk surface comprises a plurality of data zones, each data zone having a data transfer rate; a plurality of heads, wherein each head is configured to write data to a respective one of the disk surfaces; and a controller configured to operate the plurality of heads to sequentially write a sequence of data blocks to the plurality of disk surfaces in accordance with an order of head-zone combinations ordered from highest data transfer rate to lowest data transfer rate, each head-zone combination corresponding to one of the heads and one of the data zones of the respective disk surface.

Systems and methods for improving sequential data rate performance using sorted data zones

A multi-head disk drive is disclosed comprising a plurality of disk surfaces, and a head assembly comprising a plurality of heads, wherein each disk surface comprises a plurality of data zones, and each data zone having a data transfer rate different from the other zones of the respective disk surface. A controller is operable to sequentially write a sequence of data blocks to the plurality of disk surfaces in accordance with a list of head-zone combinations, each head-zone combination corresponding to one of the heads and one of the data zones of the respective disk surface. The head-zone combinations in the list are ordered from highest data transfer rate to lowest data transfer rate, and each disk surface comprises a pivot point defining a direction of writing data in the data zones from one of an outer diameter toward a middle diameter and an inner diameter toward the middle diameter.

Systems and methods for improving sequential data rate performance using sorted data zones for butterfly format

An information processing apparatus having an address translation system includes a plurality of processors in each of which an addressing is carried out by translating a logical address into a real address in the virtual storage system for data processing. The plurality of processors include a scalar processor for translating a logical address into a real address by using an address translation table; and a vector processor for determining if the logical address to be relocated lies within a predetermined address range, for address-relocating the logical address to the real address based on a relocation table when the logical address lies within the predetermined address range, and using the logical address as a real address when the logical address lies outside of the predetermined address range. The predetermined address range and the content of the relocation table are set by the scalar processor which supervises the program storage area.

Address conversion for a multiprocessor system having scalar and vector processors

In a pipeline arithmetic apparatus, an arithmetic operation is divided into a plurality of stages and processed in an overlapping manner in each of the stages. Arithmetic circuits are provided each in association with each stage. Registers hold control information indicating the contents of arithmetic operations to the individual arithmetic circuits or to a predetermined number of the arithmetic circuits, respectively. The control information held by each of the registers is supplied to the associated arithmetic circuit or circuits straight-forwardly or after having been decoded to command the arithmetic operation to be executed by each of the arithmetic circuits. The control information held by each of the registers as well as the output from each of the arithmetic circuits is transferred to the registers and the arithmetic circuits of the succeeding stages, respectively.

Pipeline arithmetic apparatus

A vector processor has a main storage, a main memory control circuit, vector registers, data transfer circuits; an address register group, and vector arithmetic units. The vector processor performs vector arithmetic processings of vector data received from the vector registers and sends the results to the vector registers. For simple vector instructions, the vector processor divides the vector processings and carries out the vector processings in parallel, using a plurality of sets of the above-mentioned data transfer circuits, vector registers and vector arithmetic units. On the other hand, for complicated vector instructions, the vector processor carries out the vector processings without dividing them using the vector registers, data transfer circuits and vector arithmetic units which were designated by the vector instructions.

Vector processor having pair process mode and single process mode

PURPOSE: To attain different kinds of operations continuously and duplicatively, by providing a register storing control information indicating the content of operation corresponding to plural operation circuits, decoding the control information in each register, and providing the information for the corresponding operating circuit. CONSTITUTION: An input operand register 1, intermediate stage latches 5, 6, and an operation result register 7 are connected to operation circuits 2W4. After an instruction register receiving control information from an instruction readout circuit 18, instruction registers 23W25 corresponding to each stage of operating circuit are provided in series, and set signals 30W32 are provided. Instruction decoders 26, 27W29 are connected to registers 20, 23, 24 and 25, and the decoders decode the control information in the registers 20, 23W25 and instructs the operation corresponding to the control information to the corresponding operation circuit. Further, the control information in each register and the output of each operation circuit are applied to the register of the next stage and the operating circuit sequentially. COPYRIGHT: (C)1983,JPO&Japio

Yasuhiko Hatakeyama

Papers

Address conversion for a multiprocessor system having scalar and vector processors

Pipeline arithmetic apparatus

Vector processor having pair process mode and single process mode

Pipeline operating device

High‐speed lan architecture based on b‐isdn technology