Placement is one of the most important physical design stages in the VLSI design flow. This step determines the locations of cell elements to get better circuit design in terms of wirelength and routability. In this paper, we propose a detailed placement and legalization algorithm under the maximum displacement constraint after the global placement stage. The flow of our algorithm includes optimal region movement, vertical swapping, reordering, and clustering. A benefit function is proposed to take into account both the wirelength and routability issues, and guide the process of each step in the algorithm. In comparison with the benefit function that considers the wirelength issue only, experimental results show that our benefit function can reduce a great deal of placement density with only a little increase in wirelength, and gets better results in terms of scaled HPWL which is composed of the half-perimeter wirelength (HPWL) and the weighted placement density issues.

Yi-Hsuan Chiu

Papers

A Detailed Placement and Legalization Method for Placement Finishing