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Design Of Analog Cmos Integrated Circuits

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

A novel, inverter-based, fully differential, body-driven, rail-to-rail, input stage topology is proposed in this paper. The input stage exploits a replica bias control loop to set the common mode current and a common mode feed-forward strategy to set its output common mode voltage. This novel cell is used to build an ultralow voltage (ULV), ultralow-power (ULP), two-stage, unbuffered operational amplifier. A dual path compensation strategy is exploited to improve the frequency response of the circuit. The amplifier has been designed in a commercial 130 nm CMOS technology from STMicroelectronics and is able to operate with a nominal supply voltage of 0.3 V and a power consumption as low as 11.4 nW, while showing about 65 dB gain, a gain bandwidth product around 3.6 kHz with a 50 pF load capacitance and a common mode rejection ratio (CMRR) in excess of 60 dB. Transistor-level simulations show that the proposed circuit outperforms most of the state of the art amplifiers in terms of the main figures of merit. The results of extensive parametric and Monte Carlo simulations have demonstrated the robustness of the proposed circuit to PVT and mismatch variations.

https://www.mdpi.com/2076-3417/11/6/2528/pdf

A 0.3 V, Rail-to-Rail, Ultralow-Power, Non-Tailed, Body-Driven, Sub-Threshold Amplifier

In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tree-based structure improves the CMRR of the proposed amplifier with respect to the conventional OTA architectures and allows achievement of a reasonable CMRR even at supply voltages as low as 0.3 V and without tail current generators which cannot be used in ULV circuits. The bias currents and the static output voltages of all the stages implementing the architecture are accurately set through the gate terminals of biasing transistors in order to guarantee good robustness against PVT variations. The proposed architecture and the implementing stages are investigated from an analytical point of view and design equations for the main performance metrics are presented to provide insight into circuit behavior. A 0.3 V supply voltage, subthreshold, ultra-low-power (ULP) OTA, based on the proposed tree-based architecture, was designed in a commercial 130 nm CMOS process. Simulation results show a dc gain higher than 52 dB with a gain-bandwidth product of about 35 kHz and reasonable values of CMRR and PSRR, even at such low supply voltages and considering mismatches. The power consumption is as low as 21.89 nW and state-of-the-art small-signal and large-signal FoMs are achieved. Extensive parametric and Monte Carlo simulations show the robustness of the proposed circuit to PVT variations and mismatch. These results confirm that the proposed OTA is a good candidate to implement ULV, ULP, high performance analog building blocks for directly harvested IoT nodes.

/pdf/a-tree-based-architecture-for-high-performance-ultra-low-3sf66ewe.pdf

A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

https://iopscience.iop.org/article/10.1088/1361-6439/ac3465/pdf

Ultra-low power signal conditioning system for effective biopotential signal recording

Ultra-low-power circuits that can work under a low-voltage supply are in great demand in future wearable biomedical applications, which tend to be integrated with low-output-voltage energy harvesting devices. In this paper, we present a low-voltage low-power continuous-time low-pass filter (CT-LPF), which is indispensable in biomedical systems. When a low-voltage supply is used, it is necessary to make the output quiescent voltage ( $\text{V}_{\mathrm {Q}}$ ) stable in the LPF, otherwise the dynamic range will be reduced. Conventional Source-follower (SF) based topologies can achieve ultra-low-power consumption. However, the difference of the input and output $\text{V}_{\mathrm {Q}}$ is sensitive to process and temperature variations. In this work, a complementary SF based topology with a bulk-common-mode-feedback (B-CMFB) circuit is proposed to keep the output $\text{V}_{\mathrm {Q}}$ tracking the input $\text{V}_{\mathrm {Q}}$ and immune to the process and temperature variations. A 4th-order LPF using the proposed topology has been implemented in a standard $0.18~\mu \text{m}$ CMOS process, which achieves a power consumption of only 3.69-nW under a 0.5-V voltage supply with a bandwidth of 200 Hz. Measurement results show that the input-referred noise is $91.9~\mu \text{V}_{\mathrm {rms}}$ . The IIP3 is 5.0 dBm and the dynamic range (DR) is 48.5 dB. The active chip area is only 0.074 mm2. The proposed LPF achieves both ultra-low power consumption with a 0.5-V supply and a stable output $\text{V}_{\mathrm {Q}}$ immune to process and temperature variations, which is suitable for low-supply-voltage biomedical systems.

A 0.5-V 3.69-nW Complementary Source-Follower-C Based Low-Pass Filter for Wearable Biomedical Applications

This paper presents an 8-bit calibration-free LO-path phase shifter (PS) for large scale 28 GHz phased-array transceiver. To overcome the nonlinearity of a vector-summing PS, two 8-bit digitally-controlled variable gain amplifier are utilized to generate high linearity amplitude modulation. Three transformers cooperating with a parallel resonator are developed to sum the I/Q signal as well as provide a fine isolation between I/Q path, thus provide a high linearity vector summation. Simulation results show that the PS achieves 360° phase shift with 8-bit resolution and a RMS phase error of 0.51°. The INL and DNL of phase-shifting is +0.66°/-0.83° and +0.22°/-0.19° respectively. Implemented in TSMC 40 nm LP process, the chip occupies an active area of 0.18 mm2 and consumes 28.6 mW from 1.1 V supply voltage.

A 28 GHz 8-Bit Calibration-Free LO-Path Phase Shifter using Transformer-Based Vector Summing Topology in 40 nm CMOS

In wearable biomedical applications, a constant dc common-mode (CM) voltage of low-pass filters (LPFs) is needed to boost the dynamic range when low supply voltage is used for high power efficiency. Traditional source-follower based LPFs consume very low power but introduce a CM voltage difference between input and output. This paper presents an ultra-low-power LPF, which features a source-follower based topology with a bulk-feedback technique. The bulk-feedback technique is proposed to keep a constant dc CM voltage, which is robust to process and temperature variations. In order to validate the proposed concept, a fourth-order LPF has been designed as a prototype. Implemented in a TSMC 180 nm CMOS process, the filter occupies an active area of only 0.048 mm2. Simulation results show that the filter consumes 9.0-nW static power from a 0.5-V voltage supply when the cutoff frequency is set to about 200 Hz. The filter achieves an input-referred noise in −3 dB bandwidth of 41.21 µVrms and an in-band IIP3 of 4.0 dBV, which corresponds to a spurious free dynamic range (SFDR) of 61.1 dB. The proposed LPF achieves a competitive FOM among the reported works.

A 0.5-V Ultra-Low-Power Low-Pass Filter with a Bulk-Feedback Technique

A 12-bit 0.5–2.4-GHz parasitic-insensitive digital-to-phase converter (DPC) with high linearity is presented in this letter. A modified parasitic-insensitive charge-based (PICB) phase interpolator (PI) is proposed to avoid linearity degradation caused by parasitic effect. A novel PI cell with separated clock selecting logic is implemented to solve charge leakage and overcharging problem. The DPC is designed and fabricated in 40-nm CMOS technology, which occupies a chip area of 0.04 mm2 and consumes 18.3 mW from a 1.3-V supply voltage. Operating in a frequency range from 0.5 to 2.4 GHz, the DPC demonstrates a peak integral nonlinearity (INL) of 0.65° and a peak differential nonlinearity (DNL) of 0.25°.

A 12-Bit 0.5–2.4-GHz 0.65°-Peak-INL Parasitic-Insensitive Digital-to-Phase Converter

This paper presents a CMOS fully-integrated temperature sensor based on a relaxation oscillator for IoT applications. To reduce power consumption, this sensor utilizes the half-period pre-charge compensation relaxation oscillator and uses a time-to-digital convertor (TDC) instead of analog-to-digital convertor (ADC) to count. Besides, the current distribution circuit is employed to improve temperature accuracy. The proposed sensor is implemented in 0.18 µm CMOS and occupies an area of 0.11 mm2. Measurement results show that the temperature sensor achieves an inaccuracy of −0.3/+0.27 °C across −15°C to 65°C after 2-point calibration. The chip consumes 1.3 µW at 27°C with a 650 mV voltage supply.

Yi Tan

Papers

A 0.5-V 3.69-nW Complementary Source-Follower-C Based Low-Pass Filter for Wearable Biomedical Applications

A 28 GHz 8-Bit Calibration-Free LO-Path Phase Shifter using Transformer-Based Vector Summing Topology in 40 nm CMOS

A 0.5-V Ultra-Low-Power Low-Pass Filter with a Bulk-Feedback Technique

A 12-Bit 0.5–2.4-GHz 0.65°-Peak-INL Parasitic-Insensitive Digital-to-Phase Converter

A 1.3-µW −0.3/+0.27°C Inaccuracy Fully-integrated Temperature Sensor Based on a Pre-Charge Relaxation Oscillator for IoT applications