VLSI Floor-planning is known to be a NP hard problem. Therefore, most of the EDA tools use heuristic algorithms to solve this problem that yield near optimal solutions. Simulated annealing has been known to produce good results in floor planning. However, the results of simulated annealing can be biased by the initial placement of the modules. In this paper we study the effect of initial placement on the floor planning. The method can be used on slicing and non- slicing floor-plans. The proposed algorithm uses the number of blocks as specified in Microelectronics Centre of North Carolina (MCNC) benchmark circuits. The results are obtained for different configurations of a single floor plan and the best floor-plan is chosen as a near optimal solution.

Effect of Module Order on VLSI Floor Planning using Simulated Annealing

With the development of integrated circuit technology, especially after the feature size of integrated circuit has entered the deep submicron stage, the use of many similar technologies, such as optical proximity effect correction (OPC), phase shift mask (PSM) and so on, makes the manufacturing cost of integrated circuits increase sharply. Multi-project wafers (MPW) stream multiple IC designs using the same process on the same wafer, and the IC designs participating in the same multi-project wafer project share the cost of taping according to the area and so on. Most of the existing methods are difficult to represent arbitrary polygon layout, and it is not convenient to design machine learning optimization goals. In this paper, we propose a layout optimization methodology based on machine learning framework to solve the splicing problem of MPW. The polygons are cut into rectangle and represented in Euclidean space, so that the minimum splicing area between chips can be achieved through gradient descent optimization and simulated annealing. The experiment results indicate that the proposed PCB routing method can obtain more than 95% area utilization, while the aspect ratio is approximately 1.

A MPW splicing algorithm based on machine learning

A transformation algorithm to construct a rectangular floorplan

VLSI Floorplan Area Optimization using Swarm Intelligence

Floorplanning is an indispensable step in very large scale integration (VLSI) design flow. Fixed-outline floorplanning is a challenging problem because it requires additional constraint that the floorplanning must meet both width and height criteria. In this paper, a modified simulated annealing (MSA) algorithm is presented with a new cost function for this problem. In our algorithm, a two-step strategy is used to improve the efficiency of the algorithm and balance the main function and secondary function. In addition, a local search strategy is employed to make sure a feasible solution can be found. Experimental results indicate that the success rate of each benchmark is 100% in deferent aspect ratio

Yifan Weng

Papers

A Modified Multi-objective Simulated Annealing Algorithm for Fixed-outline Floorplanning