This paper proposes a scalable and efficient frequency multiplication technique that synthesizes a multi-phase clock with finely adjustable output taps. It uses a pulse injection locked rotary traveling-wave oscillator (RTWO) with switched capacitors and complementary varactor pairs to achieve a 1.7–2-GHz tuning range and to implement the fine phase adjustment. The worst case phase-tuning resolution is 0.36°. The design is implemented in IBM’s 130-nm CMOS technology, and consumes a total power of 28.4 mW. Locked to a clean 679-MHz reference, it has a phase-noise performance of $-{\text {132 dBc/Hz}}$ at 100-kHz offset from 2.039 GHz. It achieves 39-fs integrated root mean square (rms) jitter from 1 kHz to 40-MHz offset, for a ${\text {Jitter}}^{2} \ast {\text {Power Figure of Merit}}$ (FOM) of $-{\text {251 dB}}$ .

A 2-GHz Pulse Injection-Locked Rotary Traveling-Wave Oscillator

This paper presents the integration of resonant clocking to multi-die architectures to synchronize individual chiplets connected through an active silicon interposer. The proposed inter-chiplet synchronization through the active silicon interposer rotary oscillator array (ASI-ROA) provides a unitary clock domain to the multiple die (i.e. multiple chiplets) in the package with a very low design overhead. System performance analysis is performed with parasitics-extracted, post-layout simulation models of two different sizes of representative heterogeneous multi-die architectures, each with varying number of RISC-V cores per die. Each RISC-V core of the multi-die package belongs to the unitary clock domain, designed with ASI-ROA to operate at a frequency of 2 GHz. The proposed architecture is investigated for robustness in frequency and skew across the multi-die system (MDS) with SPICE based simulations of post layout models, demonstrating variations of only 80 MHz for a 2 GHz target frequency. The power savings are upto 41% for the overall MDS, compared to an equivalent implementation with a contemporary ADPLL used to synchronize the multiple chiplets over the active interposer. The average clock skew of the completely resonant architecture presented in this work is 8.2 ps.

Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems

In this paper, a brick-based rotary oscillator array (ROA) synchronization scheme is proposed, which directs all the rotary traveling wave oscillators (RTWOs) in the ROA to rotate in a pre-determined direction. This synchronization scheme increases the speed of the ROA synchronization process by eliminating the repetitive start-up trials due to start-ups from incorrect points on the oscillatory array. Simulation results confirm the effectiveness of the ROA synchronization scheme. Furthermore, the synchronization scheme is applied to an ROA-based clock generation and distribution network designed for an ISPD 10 clock benchmark in order to demonstrate its application at a larger scale.

Synchronization scheme for brick-based rotary oscillator arrays

This paper presents a topology-based solution for a low-skew rotary oscillator array (ROA) clock distribution network design. An ROA-brick structure is proposed that limits the traveling wave oscillation to only two uniform ring rotation directions in the ROA-brick: all the rings in clockwise (CW) direction or all the rings in counter CW direction. An ROA built from the ROA-bricks has the following advantages: 1) similar to the ROA-brick, only two uniform ring rotation directions are feasible in the ROA; 2) the same phase tapping points of all the rings in the ROA are identifiable; and 3) these same phase tapping points of the ROA are independent from the two possible rotation directions. It is mathematically proved that the ROA-brick is the only ROA structure, which can limit the ring rotation direction combinations so as to guarantee the generation of same phase clock signals. The proposed brick-based ROA clock generation and distribution networks are designed for ISPD 10 clock benchmarks demonstrating the gigahertz operation with the low-skew clock generation and distributions through HSPICE.

ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design

The clock buffer polarity assignment is one of the effective design schemes to mitigate the power/ground noise caused by the clock signal propagation in high-speed digital systems. This paper overcomes a set of fundamental limitations of the conventional clock buffer polarity assignment methods, which are: 1) the unawareness of the signal delay (i.e., arrival time) differences to the leaf clock buffering elements; 2) the ignorance of the effect of the current fluctuation of nonleaf clock buffering elements on the total peak current waveform; and 3) the inability of supporting low-power digital designs with multiple (dynamically operating) power modes. Clearly, not addressing 1 and 2 in the polarity assignment may cause a severe inaccuracy on the peak current estimation, which results in unnecessarily high peak current. Moreover, without tackling 3, designs may suffer from clock skew violation in some of the power modes, affecting circuit speed or reliability. To overcome the limitations, we propose a completely new fine-grained approach to the clock buffer polarity assignment combined with buffer sizing, formulating the problem into a multiobjective shortest path problem and solving it effectively for designs with a single power mode, while exploiting the flexibility of our multiobjective shortest path formulation for designs with multiple power modes. Through experiments using benchmark circuits, it is shown that the proposed approach is able to produce designs with 17% lower peak current and 20% lower power noise on average, compared with the results produced by the best ever known method.

A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems

This paper presents a unique rotary oscillator array (ROA) topology---the sparse-ROA (SROA). The SROA eliminates the need for redundant rings in a typical, meshlike rotary topology optimizing the global distribution network of the resonant clocking technology. To this end, a design methodology is proposed for SROA construction based on the distribution of the synchronous components. The methodology eliminates the redundant rings of the ROA and reduces the tapping wirelength, which leads to a power saving of 32.1%. Furthermore, a skew control function is implemented into the SROA design methodology as a part of the optimization of the connections among tapping points and subtree roots. This control function leads to a clock skew reduction of 47.1% compared to a square-shaped ROA network design, which is verified through HSPICE.

Sparse-rotary oscillator array (SROA) design for power and skew reduction

This paper presents a topology design-based solution that addresses one of the major challenges in the design of Rotary Traveling Wave Oscillator (RTWO) based clock networks—the direction of oscillation. A “rotary oscillator array (ROA) brick” structure is proposed that guarantees the consistency of the rotation direction of the traveling signals on all the RTWO rings in an ROA. The ROA built from ROA bricks has the following advantages: (1) The same phase point of all the RTWO rings in the array can easily be tracked, (2) The same phase points of the ROA are independent of the specific rotation direction of the traveling signals on the ROA. SPICE simulations demonstrate these advantages of the brick-based ROA circuit design in establishing the directional consistency of the RTWO rings.

ROA-brick topology for rotary resonant clocks

A rotary traveling wave oscillator (RTWO) frequency divider design methodology is proposed for dynamic frequency scaling. The proposed methodology can be used for designing dividers for integer division ratios of 3 to 9 within one circuit topology. HSPICE-based experiments are performed to test the electrical characteristics of the RTWO frequency dividers. The simulation results show that the power consumption of a frequency divider is as low as approximately 5mW for different frequency division ratios.

Ying Teng

Papers

Synchronization scheme for brick-based rotary oscillator arrays

ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design

Sparse-rotary oscillator array (SROA) design for power and skew reduction

ROA-brick topology for rotary resonant clocks

Resonant frequency divider design methodology for dynamic frequency scaling