A semiconductor device includes a via structure and a conductive structure. The via structure has a surface with a planar portion and a protrusion portion. The conductive structure is formed over at least part of the planar portion and not over at least part of the protrusion portion of the via structure. For example, the conductive structure is formed only onto the planar portion and not onto any of the protrusion portion for forming high quality connection between the conductive structure and the via structure.

Semiconductor Device and Method of Fabricating the Same

A mask is formed selectively on a crystalline silicon film containing a catalyst element, and an amorphous silicon film is formed so as to cover the mask. Phosphorus is implanted into the amorphous silicon film and the portion of the crystalline silicon film which is not covered with the mask. The silicon films are then heated by rapid thermal annealing (RTA). By virtue of the existence of the amorphous silicon film, the temperature of the crystalline silicon film is increased uniformly, whereby the portion of the crystalline silicon film covered with the mask is also heated sufficiently and the catalyst element existing in this region moves to the phosphorus-implanted, amorphous portion having high gettering ability. As a result, the concentration of the catalyst element is reduced in the portion of the silicon film covered with the mask. A semiconductor device is manufactured by using this portion.

Method of Manufacturing Semiconductor Device

An integrated circuit device includes a plurality of pillars protruding from a substrate in a first direction. Each of the pillars includes source/drain regions in opposite ends thereof and a channel region extending between the source/drain regions. A plurality of conductive bit lines extends on the substrate adjacent the pillars in a second direction substantially perpendicular to the first direction. A plurality of conductive shield lines extends on the substrate in the second direction such that each of the shield lines extends between adjacent ones of the bit lines. Related fabrication methods are also discussed.

Integrated circuit devices including vertical channel transistors with shield lines interposed between bit lines and methods of fabricating the same

An anisotropic silicon nitride etch provides selectivity to silicon and silicon oxide by forming a fluorohydrocarbon-containing polymer on silicon surfaces and silicon oxide surfaces. Selective fluorohydrocarbon deposition is employed to provide selectivity to non-nitride surfaces. The fluorohydrocarbon-containing polymer interacts with silicon nitride to form a volatile compound, thereby enabling etching of silicon nitride. The fluorohydrocarbon-containing polymer interacts with silicon oxide at a low reaction rate, retarding, or completely stopping, the etching of silicon oxide. The fluorohydrocarbon-containing polymer does not interact with silicon, and protects silicon from the plasma. The anisotropic silicon nitride etch can be employed to etch silicon nitride selective to silicon and silicon oxide in any dimension, including small dimensions less than 50 nm.

High selectivity nitride etch process

A forming method of an alignment mark includes: forming a multilayer structure on a substrate; forming a groove in the multilayer structure and leading the groove to penetrate through at least two layers of the multilayer structure; and filling metal materials in the groove to form a metal layer, and enclosing the metal layer to form a recess which serves as the alignment mark. The alignment mark formed with the method is deep, so that alignment accuracy degree can be improved, and manufacture yield of integrated circuits is improved.

Forming method of alignment mark

The invention provides a method for manufacturing a semiconductor device. The method comprises the following steps: providing a semiconductor substrate; sequentially forming a gate oxide layer and a floating gate polycrystalline silicon layer on the semiconductor substrate; forming a large size of floating gate buffering oxide layer on the floating gate polycrystalline silicon layer in an active zone; segmenting the large size of floating gate buffering oxide layer into a plurality of small sizes of floating gate buffering oxide layers which are identical in size; executing chemical and mechanical polishing. According to the method, a wide window is provided for a following process through optimizing the pattern of the floating gate buffering oxide layer formed on the floating gate polycrystalline silicon layer in the large-area active zone after an FGBF photolithographic process, the problem that a recess is formed in the floating gate polycrystalline silicon layer in the large-area active zone after CMP is carried out on the floating gate polycrystalline silicon layer is solved, and the whole performance of an embedded flash memory and the qualified rate of the embedded flash memory are improved.

Yinglu Wei

Papers

Method for manufacturing semiconductor device