A single-path delay feedback pipelined fast Fourier transform processor comprising at least one set of triplet FFT stage means: a first FFT stage means comprising a radix-2 butterfly, a feedback memory, and a multiplication by unity; a second FFT stage means comprising a trivial coefficient pre-multiplication, a radix-2 butterfly, a feedback memory, and a multiplication by selectable unity or Wnn/8 ; and a third FFT stage means comprising a trivial coefficient pre-multiplication, a butterfly, a feedback memory, and a complex twiddle coefficient multiplication with coefficients determined using a twiddle factor decomposition technique.

Recoded radix-2 pipelined fft processor

An FFT processor using a single delay path and a permuter provides a reduction in the implementation area and a related reduction in power consumption through efficiencies obtained by the modification of a butterfly unit and the use of a novel interleaver. The modified butterfly unit is obtained by removal of complex variable multipliers, which is possible due to the simplification of twiddle factors in the stages that correspond to the modified butterfly unit.

Pipelined fft processor with memory address interleaving

A processor for performing a Fast Fourier Transform and/or an Inverse Fast Fourier Transform of a complex input signal comprises a first stage for passing the input signal to a second stage when a Fast Fourier Transform procedure is to be performed and for swapping the real and imaginary components of the complex input signal before passing the signal to the second stage if an Inverse Fast Fourier Transform procedure is to be performed. The second stage has first and second radix-4 butterfly elements. A third stage is arranged to switch between first and second operating modes, the second operating mode being for processing a complex conjugate symmetrical input signal. A fourth stage has a plurality of processing units, one or more of the processing units comprising a radix-2 pipelined Fast Fourier Transform processor. The first and second radix-4 butterfly elements are arranged to perform a butterfly operation on the complex input signal to generate and deliver one or more components of a processed signal to the fourth stage. The fourth stage is arranged to process the processed signal received from the first stage according to a Fast Fourier Transform processing procedure to produce an output signal. There is also disclosed a method for performing a Fast Fourier Transform and/or Inverse Fast Fourier Transform of a complex input signal.

Processor and method for performing a fast fourier transform and/or an inverse fast fourier transform of a complex input signal

The present invention discloses a fast Fourier transform (FFT) processor based on multiple-path delay commutator architecture. A pipelined architecture is used and is divided into 4 stages with 8 parallel data path. Yet, only three physical computation stages are implemented. The process or uses the block floating point method to maintain the signal-to-noise ratio. Internal storage elements are required in the method to hold and switch intermediate data. With good circuit partition, the storage elements can adjust their capacity for different modes, from 16-point to 4096-point FFTs, by turning on or turning off the storage elements.

https://ir.nctu.edu.tw:443/bitstream/11536/105590/1/20080155003.pdf

Pipeline-based reconfigurable mixed-radix FFT processor

A fast fourier transform apparatus is disclosed having a simple processing structure and improved processing speed. The fast fourier transform apparatus includes a memory and an operation processing portion that classifies to-be-processed data stored in the memory into data processing groups, according to a priority value given to the plurality of radix operators based on the amount of bit processing per unit. The memory is controlled so that the to-be-processed data is processed by the radix-operators in accordance with the order of the classified data processing. An order of the classified data processing groups processed by the radix operators is recovered by re-arranging the data processing groups according to a reversing method which corresponds to the operation processing order. The radix operations and data recovery is performed by reversing the digits just one time, thereby simplifying the procedure of the operation.

Fast fourier transform apparatus

The present invention discloses a fast Fourier transform (FFT) processor using a high speed area-efficient algorithm. The FFT processor is embodied by using the algorithm including a radix-4 butterfly module for receiving four input signals, and performing a butterfly operation thereon, and a radix-2 butterfly module connected to the radix-4 butterfly module, for performing the butterfly operation on the output signals from the radix-4 butterfly module. As a result, a number of nontrivial complex multipliers is reduced, to perform the FFT in a high speed in a small area.

Yon-ho Jung

Papers

Fast fourier transform processor using high speed area-efficient algorithm