Active RF devices and their modelling nonlinear circuit simulation techniques linear RF amplifier designs linear and low-noise RF amplifiers high power RF transistor amplifier designs oscillators mixers and frequency multipliers circuits in systems.

Active circuits and systems

This paper, presents a 24GHz Amplifier circuit demonstrator designed and fabricated in 0.25μm BiCMOS mature technology from NXP Semiconductors in order to evaluate the effect of the interconnect lines on impedance matching. It features 11 dB of gain, 7.6 dB of noise figure (NF) at the working frequency. The input/output impedances are matched close to 50 Ohm with an input return loss of-12 dB and output return loss of about −13 dB. The matching methodology is improved by considering the interconnect lines (from the Layout view) in the matching networks. Schematic circuit simulations and measurements are used to evaluate the amplifier circuit performances. The results are presented here and show a good agreement between both, measurements and simulations.

LNA circuit design counting the interconnect line parasitics

In this paper, the aim is to design, simulate and fabricate a two-stage low noise amplifier circuit (LNA) with high gain and low noise figure using GaAs FET for frequency from 3.7 GHz to 4.2 GHz, which is used for C band satellite receiver systems. The most important thing in the design of the LNA is to require the trade-off many important characteristics such as: Gain, noise figure, stability, and bandwidth. The LNA uses a diagram of the two-stage cascade to create high gain and noise figure as lower as possible. All of the designed, simulated and fabricated processes were done using Agilent' ADS 2009 package and machine LPKF Promomat C40. The LNA has successfully been fabricated on Rogers FR4 type with following specifications: Maximum overall gain of 25.4 dB, operating frequency: 3.7 GHz to 4.2 GHz, noise figure is less than 1.1dB, good impedance input-and-output matching, input impedance: 50 ohm.

/pdf/design-and-fabrication-of-high-gain-low-noise-amplifier-at-4-1z7f5lfpaq.pdf

Design and Fabrication of High Gain Low Noise Amplifier at 4 GHz

In this paper, the aim is to design, simulate and fabricate a wideband low noise amplifier circuit at L band with a high gain and low noise figure. The research process was conducted from the design, simulation and layout using Advance Design System (ADS) software to build the actual circuit. The design of the low noise amplifier uses diagram of two-stage cascade amplifier with different center frequency in order to create a good wideband performance and high gain. The low noise amplifier has been fabricated on a PCB board using pHEMT FET transistor amplifier with following specifications: Maximum overall gain of 33.19 dB, operating frequency from 950MHz to 2150MHz, noise figure is about 1.29 dB, the reverse isolation of -37.42 dB, the LNA using a 5 V supply voltage respectively and total current consumptions of 20 mA. This low noise amplifier is used for Satellite Receiver. Keyword: Low noise amplifier, L band, noise figure, satellite receiver, ADS.

https://ijraset.com/fileserve.php?FID=9769

Wideband Low Noise Amplifier Design at L band for Satellite Receiver

This paper presents two-stage Low Noise Amplifier (LNA) design for BD-II (B3 mode) receiver. It presents circuit design and simulation of Low Noise Amplifier. This amplifier uses ATF54143 low noise PHEMT device. To make the two-stage LNA stability at wideband, a T-shape resistor attenuation network is innovatively added to the output of the LNA, which hardly increase the noise figure as the last stage of circuit. It also makes the output well matching and increase the isolate with the following circuit. From the simulation, the LNA keep stability at wideband, Gain achieved is 25dB with deviation less than ±0.2dB, 0.4 dB noise figure(NF) is achieved, the VSWR of input and output is less than 1.3 dB.

Yongzhong Hu

Papers

Two-stage Low Noise Amplifier for BD-II receiver application