An integrated heat sink array is introduced in SOI power devices having multiple unit cells, which can be used to reduce the temperature rise in obtaining more uniform temperature peaks for all the unit cells across the device area, so that the hot spot which is prone to breakdown can be avoided, thus the safe operating area of the device can be improved. Also the array sacrifice less area of the device, therefore results in low Rdson.

Semiconductor device with heat sinks

The present invention relates to a wafer having an alternating design structure and a method for manufacturing a semiconductor package using the wafer. The present invention is conceived to solve all the aforementioned problems associated with the related art wafer having the lattice design arrangement and method for manufacturing a semiconductor package using the wafer. According to the present invention, the number of dies per wafer can be maximized (6 to 8 % of dies per wafer can be further produced) as compared to the conventional lattice design arrangement to allow the manufacturing costs of dies to be lowered by designing the wafer to have an alternating arrangement design structure. Further, the time taken to inspect dies can be remarkably reduced through the improvement in efficiency of a die tester by allowing the die to be inspected using a carrier when manufacturing the semiconductor package. In addition, the manufacturing process can be simplified by omitting an inking process for indexing reject dies, which has been essentially performed in the related art semiconductor package manufacturing process. Furthermore, the productivity improvement and in-line automation can be achieved by mounting a carrier with dies for the handling of the dies by the carrier, thereby contributing to reduction in price of the semiconductor manufacturing equipment.

Yoon Soo Sang

Papers

Wafer having alternating design structure and method for manufacturing semiconductor package using the same