Yoshihiro Minami

TL;DR: Device simulation proves that the floating body cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant.

TL;DR: In this article, the physics of autonomous refresh of FBC is presented, where current input to the floating body by impact ionization and output by charge pumping can balance to make FBC refresh by itself without sense amplifier operation.

TL;DR: In this paper, the memory cell characteristics of the FBC (Floating Body Cell) have been experimentally verified by 0.175 /spl mu/m cell array for the first time.

Abstract: A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.

TL;DR: In this article, a dynamic latch sense amplifier/bit line replenishes "1" cells with holes lost during word line cycles and reduces the refresh busy rate, and a multi-averaging method of dummy cells over 128 pairs of "1s" and "0s" enhances the sense margin and contributes to the 18.5ns access time.