A data recovery system for a serial digital data link includes a data sampler (403), compare logic (407), a phase controller (410), and a phase shifter (413). The data sampler samples input data three times in a bit time which time is determined by clock pulses generated by the phase shifter, and recovers digital data according to a predetermined decision criterion. Data sampling phases are split so as to track the data eye. The compare logic (407) compares the output of the data sampler (403) according to a predetermined method. Phase controller (410) uses the output of the compare logic and generates phase control signals. These signals are set so as to control the sampling times of the data sampler and to attain near optimally recovered data stream. The phase shifter uses the phase control signals and makes three different phase clocks from input clock. The input clock can be an external clock, or can be recovered from the external clock or input data stream.

Data recovery using data eye tracking

The clutch cover assembly comprises a clutch cover, a pressure plate, a washer-type spring and a lever member. The clutch cover is fixed to a flywheel. The pressure plate is located within said clutch cover and is fashioned with a pressing surface for clamping facings against the flywheel. The washer-type spring engages the pressure plate to the flywheel. The lever member, supported by the clutch cover, is for engaging the pressure plate in combination with the washer-type spring to the flywheel and for releasing engaging loads of the washer-type spring from the pressure plate.

Clutch cover assembly

Data is transmitted from any one of a plurality of transmitters in synchronism with a first clock. A receiver receives the data in synchronism with the first clock and a second clock having a predetermined phase relationship with the first clock. Control information is previously held in the receiver regarding data reception conditions associated with the plurality of transmitters to control reception conditions of the receiver on the basis of the control information.

Method and system for synchronizing data having skew

It is intended to attain accurate parallel data
transmission between a plurality of synchronous circuits
operating at independent clocks, and to suppress increase
of the scale of circuit at the minimum. A synchronous
circuit controller comprises a delay section (3) for
delaying data (D11) three times with a step with amount of
delay (d1), and outputting corresponding delay data (D12-D14),
a latch section (4) for latching each of the data
(D11-D14) in synchronization with a clock (CK2), and
outputting latch data (L11-L14), a comparator circuit (5)
for comparing the latch data (L11-L14) each other in the
ascending order of the amount of delay, detecting matching
or non-matching between signals to be compared, and
outputting comparison signals (C11-C13) corresponding to
the detection results, respectively, and a selector circuit
(6) for selecting one of the data (D11-D13) as synchronous
data (DS) in response to control of the comparison signals
(C11-C13).

Synchronous circuit controller for controlling data transmission between asynchronous circuits

There is provided a transmission circuit which can certainly perform transmission of data of digital form between two circuits operating in synchronization with two clock signals having the same frequency even if phase shift is generated between the two clock signals. According to a phase difference between a clock signal CK 1 and a clock signal CK 2, the transmission circuit performs either one of an operation of outputting pre-transmission digital data inputted to the transmission circuit as it is or after it is inverted, and an operation of sampling it in synchronization with the clock signal CK 2 and outputting it as it is or after it is inverted.

Transmission circuit and semiconductor device

PURPOSE: To attain the operation of a spatial split type switch with a common clock by constituting the circuit with a clock frequency divider circuit and an elastic storage of conventional constitution so as to allow a data to take over a clock having a speed of a multiple of N and independent bit phase. CONSTITUTION: A clock frequency divider circuit 2 receives a 2nd clock 3 and outputs the clock while dividing the frequency to 1/N. A clock 1 and a data D synchronously with the clock are inputted to an elastic storage ES. With a clock 3 having a frequency at a multiple of N of the frequency of the clock 1 and independent bit phase received to the circuit 2, the frequency divider circuit 2 divides the clock frequency into the frequency the same as the frequency (1/N) of the clock 1 and the resulting signal is inputted to a terminal C2 of the elastic storage ES as the clock 2. A data synchronously with the clock 2 is outputted from a terminal Q of the elastic storage ES. The output data is naturally synchronously with the clock 3. COPYRIGHT: (C)1990,JPO&Japio

Yoshihiro Ootsuka

Papers

Bit phase synchronizing circuit