Y
Yoshio Nagahiro
Researcher at Fujitsu
Publications - 6
Citations - 308
Yoshio Nagahiro is an academic researcher from Fujitsu. The author has contributed to research in topics: Thin-film transistor & Oxide thin-film transistor. The author has an hindex of 5, co-authored 6 publications receiving 308 citations.
Papers
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Patent
Method for forming a film and method for manufacturing a thin film transistor
Matsumoto Tomotaka,Jun Inoue,Teruhiko Ichimura,Yuji Murata,Jun‐ichi Watanabe,Yoshio Nagahiro,Mari Hodate,Oki Kenichi,Masahiro Okabe +8 more
TL;DR: In this paper, an impurity containing silicon film is formed by a chemical vapor deposition method between a source electrode and a drain electrode of a thin film transistor and a silicon film connected to these electrodes, and a flow rate of impurity-containing gas is regulated so that impurity density becomes larger as approaching to the source and the drain electrode, a leakage current in an OFF-state of the transistor is reduced.
Patent
Active matrix type display
TL;DR: In this paper, the authors proposed an active matrix type display which can obtain large storage capacitors without thinning an insulating film between electrodes nor expanding an electrode to a pixel area.
Patent
Thin-film transistor, liquid-crystal display device, and method of producing the same
Hong Yong Zhang,Yoshio Nagahiro +1 more
TL;DR: In this paper, a short-circuiting pattern that shortcircuits the source region and the drain region of a TFT is added to a polysilicon pattern that constitutes the TFT.
Patent
Method of manufacturing a thin film transistor device
TL;DR: In this article, a method of thin-film transistor fabrication is described, which includes forming and patterning a semiconductor film to form first and second semiconductor films in, respectively, low-voltage driven and highvoltage-driven thin-filtered transistor formation regions.
Patent
Thin film transistor device, method of manufacturing the same and liquid crystal panel
TL;DR: In this paper, a gate insulating film of a TFT driven at a low voltage (3.3 V or 5 V) is constituted by one gate, and a thickness thereof is set to, for example, 30 nm.