We present a new type of bit-parallel non-recursive Karatsuba multiplier over $GF(2^m)$ generated by an arbitrary irreducible trinomial. This design effectively exploits Mastrovito approach and shifted polynomial basis (SPB) to reduce the time complexity and Karatsuba algorithm to reduce its space complexity. We show that this type of multiplier is only one $T_X$ slower than the fastest bit-parallel multiplier for all trinomials, where $T_X$ is the delay of one 2-input XOR gate. Meanwhile, its space complexity is roughly 3/4 of those multipliers. To the best of our knowledge, it is the first time that our scheme has reached such a time delay bound. This result outperforms previously proposed non-recursive Karatsuba multipliers.

Mastrovito Form of Non-Recursive Karatsuba Multiplier for All Trinomials

Cryptographic algorithms implemented on smart-cards must be protected against side-channel attacks. Some encryption schemes and hash functions like IDEA, RC6, MD5, SHA-1 alternate various arithmetic and boolean operations, each of them requiring a different kind of blinding. Hence the maskings have to be changed frequently. How to switch reasonably between standard arithmetic masking and boolean masking was shown in [2], [3], [5] and [9]. In this paper we propose more space-efficient table-based conversion methods. Furthermore, we deal with some non-standard arithmetic operations, namely arithmetic modulo 2 k + 1 for some k ∈ IN and a special multiplication used by IDEA.

Switching blindings with a view towards IDEA

New bit-parallel Montgomery multiplier for trinomials using squaring operation

Shifted polynomial basis (SPB) and generalized polynomial basis (GPB) are two efficient bases of representation in binary extension fields, and are widely studied. In this paper, we use the GPB formulation to derive a new modified SPB (MSPB) representation for arbitrary irreducible trinomials and pentanomials. It is shown that the basis conversion from the MSPB to the SPB for trinomials is free of hardware cost. We have shown that multiplication based on SPB and MSPB representations can make use of Toeplitz matrix–vector product (TMVP) formulation. The existing TMVP block recombination (TMVPBR) approach is used here to derive an efficient $k$ -partitioning TMVPBR decomposition for digit-serial double basis multiplication that can achieve subquadratic space complexity. From synthesis results, we have shown that the proposed multiplier has less area and less area-delay product compared with the existing digit-serial multipliers. We also show that the proposed multiplier using $k$ -partitioning TMVPBR decomposition can provide a better tradeoff between time and space complexities.

Area-Delay Efficient Digit-Serial Multiplier Based on $k$ -Partitioning Scheme Combined With TMVP Block Recombination Approach

Biological cells require active fluxes of matter to maintain their internal organization and perform multiple tasks to live. In particular they rely on cytoskeletal transport driven by motor proteins, ATP-fueled molecular engines, for delivering vesicles and biochemically active cargoes inside the cytoplasm. Experimental progress allows nowadays quantitative studies describing intracellular transport phenomena down to the nanometric scale of single molecules. Theoretical approaches face the challenge of modelling the multiscale, out-of-equilibrium and non-linear properties of cytoskeletal transport: from the mechanochemical complexity of a single molecular motor up to the collective transport on cellular scales. We will present some of our recent progress in building a generic modelling scheme for cytoskeletal transport based on lattice gas models called “exclusion processes”. Interesting new properties arise from the emergence of density inhomogeneities of particles along the network of one dimensional lattices. Moreover, understanding these processes on networks can provide important hints for other fundamental and applied problems such as vehicular, pedestrian and data traffic, or ultimately for technological and biomedical applications.

The Impact of Applications on Mathematics

Koc and Sunar proposed an architecture of the Mastrovito multiplier for the irreducible trinomial f(x)=xn+xk+1, where k ≠ n/2 to reduce the time complexity. Also, many multipliers based on the Karatsuba-Ofman algorithm (KOA) was proposed that sacrificed time efficiency for low space complexity. In this paper, a new multiplication formula which is a variant of KOA presented. We also provide a straightforward architecture of a non-pipelined bit-parallel multiplier using the new formula. The proposed multiplier has lower space complexity than and comparable time complexity to previous Mastrovito multipliers' for all irreducible trinomials.

New Bit Parallel Multiplier With Low Space Complexity for All Irreducible Trinomials Over $GF(2^{n})$

This paper proposes an efficient masking method for the block cipher SEED that is standardized in Korea. The nonlinear parts of SEED consist of two S-boxes and modular additions. However, the masked version of these nonlinear parts requires excessive RAM usage and a large number of operations. Protecting SEED by the general masking method requires 512 bytes of RAM corresponding to masked S-boxes and a large number of operations corresponding to the masked addition. This paper proposes a new-style masked S-box which can reduce the amount of operations of the masking addition process as well as the RAM usage. The proposed masked SEED, equipped with the new-style masked S-box, reduces the RAM requirements to 288 bytes, and it also reduces the processing time by 38% compared with the masked SEED using the general masked S-box. The proposed method also applies to other block ciphers with the same nonlinear operations.

https://onlinelibrary.wiley.com/doi/pdf/10.4218/etrij.11.1510.0112

Efficient masked implementation for SEED based on combined masking

In the recent years, power attacks were widely investigated, and so various countermeasures have been proposed. In the case of block ciphers, masking methods that blind the intermediate results in the algorithm computations(encryption, decryption) are well-known. In case of SEED block cipher, it uses 32 bit arithmetic addition and S-box operations as non-linear operations. Therefore the masking type conversion operations, which require some operating time and memory, are required to satisfy the masking method of all non-linear operations. In this paper, we propose a new masked S-boxes that can minimize the number of the masking type conversion operation. Moreover we construct just one masked S-box table and propose a new formula that can compute the other masked S-box's output by using this S-box table. Therefore the memory requirements for masked S-boxes are reduced to half of the existing masking method's one.

Efficient Masking Method to Protect SEED Against Power Analysis Attack

Finite fields are widely applied to ECC and cryptographic area, so many of researchers interested in efficient finite field arithmetic In particular, it is efficient to use the normal basis in hardware implementation Using the fact that the finite field GF(2m) is the subfield of GF(2mk) when GF(2mk) has the type-I optimal normal basis, in this paper, we propose a new multiplier Comparing the complexity of the proposed multiplier with Reyhani-Masoleh's multiplier proposed in 2006 which is faster, and has smaller number of XOR gates than the existing multipliers, the number of XOR gates of the multiplier is equal to that of ours for k=4,6 and 10, the XOR critical path delay, however, is more than that of the proposed one by 20% for k=10

Modified Sequential Multipliers for Type-k Gaussian Normal Bases

The FIPS 186-2 standard recommends five prime fields with a modulus so-called NIST primes for elliptic curve cryptosystems. Primes of the special form such as NIST primes have a property yields modular reduction algorithms that are significantly fast. However the number of NIST primes are not large enough. In this paper, we further extend the idea of NIST primes. Then we find more primes can provide fast modular reduction computation that NIST prime family does not support. Our method provides more efficient modular arithmetic than Montgomery algorithm in prime fields that NIST primes does not support.

Young In Cho

Papers

New Bit Parallel Multiplier With Low Space Complexity for All Irreducible Trinomials Over $GF(2^{n})$

Efficient masked implementation for SEED based on combined masking

Efficient Masking Method to Protect SEED Against Power Analysis Attack

Modified Sequential Multipliers for Type-k Gaussian Normal Bases

Extended NIST Prime Family for Efficient Modular Reduction