A performance evaluation of a level-crossing analog-to-digital converter (ADC) is presented. It is shown that its signal-to-noise ratio (SNR) does not depend on the input-signal amplitude, which results in an almost-flat SNR for amplitudes that fall into the Nyquist criteria for irregular sampling. The influence of the reconstruction procedure on SNR is discussed, and possible limitations due to the comparator and clock on the performance of the ADC are analyzed. This analysis allows for specification of comparator and clock parameters such that they do not limit the ADC performance yet are not overestimated. In conclusion, a previously known level-crossing ADC design procedure is extended. A level-crossing ADC design example is given for intended use in an ultrasound application with a frequency band from 1 to 10 MHz. MATLAB and Cadence simulations, which utilize the data obtained from a real comparator and clock, are presented, and the performance of such a level-crossing ADC is compared with a conventional ADC.

Level-Crossing ADC Performance Evaluation Toward Ultrasound Application

A process, voltage, and temperature (PVT) sensor without a voltage/current analog-to-digital converter (ADC) or bandgap reference is proposed for high accuracy, low power, and wide voltage range portable applications. Conventional temperature sensors rely on voltage/current ADC for digital output code conversion. The proposed temperature sensor generates a clock frequency proportional to the measured temperature, and converts the frequency into a corresponding digital code. The generated digital code is still under the influence of PVT variations. Two distinct sensors for voltage and process monitoring are also proposed to enhance temperature sensor environmental variation immunity. The property of zero temperature coefficient (ZTC) bias point is used to remove temperature effect. The proposed wide voltage range low power PVT sensor is designed in UMC 65nm bulk CMOS technology. It is capable of operating over a wide voltage range within 0.3V~1V. The power consumption is no more than 3.7μW at 0.3V supply voltage and a high sample rate of 10k samples/sec. The temperature error is merely −0.8~0.8oC.

Fully on-chip temperature, process, and voltage sensors

This work describes a 10-b multibit-per-stage pipelined CMOS analog-to-digital converter (ADC) incorporating the merged-capacitor switching (MCS) technique. The proposed MCS technique improves the signal processing speed and resolution of the ADC by reducing the required number of unit capacitors by half in comparison to a conventional ADC. The ADC resolution based on the proposed MCS technique can be extended further by employing a commutated feedback-capacitor switching (CFCS) technique. The prototype ADC achieves better than 53-dB signal-to-noise-and-distortion ratio (SNDR) at 120 MSample/s and 54-dB SNDR and 68-dB spurious-free dynamic range (SFDR) for input frequencies up to Nyquist at 100 MSample/s. The measured differential and integral nonlinearities of the prototype are within /spl plusmn/0.40 LSB and /spl plusmn/0.48 LSB, respectively. The ADC fabricated in a 0.25-/spl mu/m CMOS occupies 3.6 mm/sup 2/ of active die area and consumes 208 mW under a 2.5-V power supply.

/pdf/a-2-5-v-10-b-120-msample-s-cmos-pipelined-adc-based-on-3m2qiosmr2.pdf

A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching

This work describes a 10-b 150-MSample/s 4-b-per-stage single-channel CMOS pipelined ADC incorporating improved gate-bootstrapping techniques for a wideband SHA and temperature- and supply-insensitive CMOS references. The proposed ADC is designed and fabricated in a 0.18-/spl mu/m one-poly six-metal CMOS technology. The measured differential and integral nonlinearities are within 0.69 LSB and 1.50 LSB, respectively. The prototype ADC shows a peak signal-to-noise-and-distortion ratio (SNDR) of 52 dB at 150 MSample/s. The ADC maintains the SNDR over 52 dB and 43 dB, respectively, for input frequencies up to the Nyquist frequency and 400 MHz at 140 MSample/s. The active die area is 2.2 mm/sup 2/ and the chip consumes 123 mW at 150 MSample/s.

A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter with 400-MHz input bandwidth

The virtual ground reference buffer (VGRB) technique is introduced as a means to improve the performance of switched-capacitor circuits. The technique enhances the performance by improving the feedback factor of the op-amp without affecting the signal gain. The bootstrapping action of the level-shifting buffers relaxes key op-amp performance requirements including unity-gain bandwidth, noise, open-loop gain and offset compared with conventional circuits. This reduces the design complexity and the power consumption of op-amp based circuits. Based on this technique, a 12 b pipelined ADC is implemented in 65 nm CMOS that achieves 67.0 dB SNDR at 250 MS/s and consumes 49.7 mW of power from a 1.2 V power supply.

/pdf/a-12b-250-ms-s-pipelined-adc-with-virtual-ground-reference-2z933xnbzb.pdf

A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers

This work proposes an 11b 70MHz CMOS pipelined A/D converter (ADC) as one of core circuit blocks for high-speed VDSL system applications. The proposed ADC for the internal use has the strictly limited number of externally connected I/O pins while the ADC employs on-chip CMOS current/voltage (I/V) references and a merged-capacitor switching (MCS) technique to improve ADC performances. The ADC implemented in a 0.18µm n-well single-poly quad-metal CMOS technology shows the maximum SNDR of 60 dB at 70 MSample/s. The ADC maintains the SNDR of 58 dB and the SFDR of 68 dB for input frequencies up to the Nyquist rate at 60 MSample/s. The measured DNL and INL of the ADC are within ±0.63 and ±1.21 LSB, respectively. The active chip area is 1.2 mm2and the ADC consumes 49 mW at 70 MSample/s at a 1.8 V supply.

Young-Jong Lee

Papers

An 11b 70 MHz 1.2 mm 2 49mW 0.18 um CMOS ADC with on–chip current/voltage references

Young-Jong Lee

Papers

An 11b 70 MHz 1.2 mm 2 49mW 0.18 um CMOS ADC with on&#8211;chip current/voltage references

An 11b 70 MHz 1.2 mm 2 49mW 0.18 um CMOS ADC with on–chip current/voltage references