High speed signal processing depends critically on parallel processor technology. In most applications, general-purpose parallel computers cannot offer satisfactory real-time processing speed due to severe system overhead. Therefore, for real-time digital signal processing (DSP) systems, special-purpose array processors have become the only appealing alternative. In designing or using such array Processors, most signal processing algorithms share the critical attributes of regularity, recursiveness, and local communication. These properties are effectively exploited in innovative systolic and wavefront array processors. These arrays maximize the strength of very large scale integration (VLSI) in terms of intensive and pipelined computing, and yet circumvent its main limitation on communication. The application domain of such array processors covers a very broad range, including digital filtering, spectrum estimation, adaptive array processing, image/vision processing, and seismic and tomographic signal processing, This article provides a general overview of VLSI array processors and a unified treatment from algorithm, architecture, and application perspectives.

VLSI Array processors

The evolution of CORDIC, an iterative arithmetic computing algorithm capable of evaluating various elementary functions using a unified shift-and-add approach, and of CORDIC processors is reviewed. A method to utilize a CORDIC processor array to implement digital signal processing algorithms is presented. The approach is to reformulate existing DSP algorithms so that they are suitable for implementation with an array performing circular or hyperbolic rotation operations. Three categories of algorithm are surveyed: linear transformations, digital filters, and matrix-based DSP algorithms. >

CORDIC-based VLSI architectures for digital signal processing

This paper describes the development of a wavefront-based language and architecture for a programmable special-purpose multiprocessor array. Based on the notion of computational wavefront, the hardware of the processor array is designed to provide a computing medium that preserves the key properties of the wavefront. In conjunction, a wavefront language (MDFL) is introduced that drastically reduces the complexity of the description of parallel algorithms and simulates the wavefront propagation across the computing network. Together, the hardware and the language lead to a programmable wavefront array processor (WAP). The WAP blends the advantages of the dedicated systolic array and the general-purpose data-flow machine, and provides a powerful tool for the high-speed execution of a large class of matrix operations and related algorithms which have widespread applications.

Wavefront Array Processor: Language, Architecture, and Applications

An impulsive normal traction is applied uniformly over the surface of a perfectly stratified plane layered earth. The ensuing particle velocity at the surface is assumed to be measured. The problem...

The One-Dimensional Inverse Problem of Reflection Seismology

In a block transmission system the information symbols are arranged in the form of blocks separated by known symbols. Such a system is suitable for communication over time-dispersive channels subject to fast time-variations, e,g., the HF channel. The known reliable receiver for this system is the nonlinear data-directed estimator (NDDE). This paper presents appropriate equalization methods for this system. A nonstationary innovations representation based on Cholesky factorization is used in order to define a noise whitener and a maximum-likelihood block detector. Also block linear equalizers and block decision-feedback equalizers are derived. For each type we give the zero-forcing and the minimum-mean-squared-error versions. Performance evaluations and comparisons are given. We show that they perform better than conventional equalizers. As compared to the NDDE, the derived block decision-feedback equalizers perform better and are much less complex. Whereas the NDDE uses the Levinson algorithm to solve M/2 Toeplitz systems of decreasing order (where M is the number of symbols per block), the derived equalizers need to process only one Toeplitz system. Moreover, the Schur algorithm, proposed for Cholesky factorization allows us to further reduce the complexity. >

Channel equalization for block transmission systems

The design of VLSI parallel processors requires a fundamental understanding of the parallel computing algorithm and an appreciation of the implementational constraint on communications. Based on such consideration, this paper develops a highly concurrent Toeplitz system solver, featuring maximum parallelism and localized communication. More precisely, a highly parallel algorithm is proposed which achieves O(N) computing time with a linear array of O(N) processors. This compares very favorably to the O(N \log_{2} N) computing time attainable with the traditional Levinson algorithm implemented in parallel. Furthermore, to comply with the communication constraint, a pipelined processor architecture is proposed which uses only localized interconnections and yet retains the maximum parallelism attainable.

Yu Hu

Papers

A highly concurrent algorithm and pipeleined architecture for solving Toeplitz systems