Showing papers by "Yu Hu published in 2004"
01 Jan 2004
TL;DR: A 3-step heuristic, named FORst, to tackle the OARSMT problem, which has been implemented and tested and can tackle large scale nets among complex obstacles, such as a net with 1000 terminals in the presence of 100 rectangular obstacles.
Abstract: Macro cells, IP blocks, and pre-routed nets are often regarded as obstacles in VLSI routing phase. Obstacle-avoiding rectilinear Steiner minimum tree (OARSMT) algorithms are often used to meet the needs of practical routing applications. However, OARSMT algorithms with multi-terminal nets routing still can not satisfy the requirements of practical applications. This paper presents a 3-step heuristic, named FORst, to tackle the OARSMT problem. In Step1, we partition all terminals into some subsets in the presence of obstacles. Then in Step2, we connect terminals in each connected graph with one or more trees, respectively. In Step3, we connect the forest consisting of trees constructed in Step2 into a completed Steiner tree spanning all terminals while avoiding all obstacles. Two algorithms, called ACO-RSMT and GFST-RSMT, are proposed to construct OARSMT in a connected graph in Step2, which are suitable for difierent situations. This algorithm has been implemented and tested on cases with typical obstacles. The experimental results show that FORst is with great e‐ciency and can get good performance. Moreover, it can tackle large scale nets among complex obstacles, such as a net with 1000 terminals in the presence of 100 rectangular obstacles.
38 citations
27 Jun 2004
TL;DR: This paper presents a practical heuristic for RSMT construction based on ant colony optimization (ACO), which can get a very short run time and keep the high performance.
Abstract: The rectilinear Steiner minimum tree (RSMT) problem is one of the fundamental problems in physical design, especially in routing, which is known to be NP-complete. This paper presents a practical heuristic for RSMT construction based on ant colony optimization (ACO). This algorithm has been implemented on a Sun workstation with Unix operating system and the results have been compared with the GeoSteiner 3.1 and a recent work using batched greedy triple construction (BGTC). Experimental results show that our algorithm, named ACO-Steiner, can get a very short run time and keep the high performance.
19 citations
10 Oct 2004
TL;DR: This paper addresses the problem of test response compaction by proposing a single-output encoder based on check matrix of a (n, n-1, m, 3) convolutional code and some experimental results would verify the efficiency of the proposed optimized algorithm.
Abstract: This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output encoder based on check matrix of a (n, n-1, m, 3) convolutional code is presented. When the proposed four theorems are satisfied, the encoder can avoid two and any odd erroneous bit cancellations, handle one unknown bit (X bit) and diagnose one erroneous bit. Two types of encoders are proposed to implement the check matrix of the convolutional code. A large number of X bits can be tolerated by choosing a proper memory size and weight of check matrix, which can also be obtained by an optimized input assignment algorithm. Some experimental results would verify the efficiency of the proposed optimized algorithm.
8 citations
15 Nov 2004
TL;DR: A parallel core wrapper design (pCWD) approach is presented in this paper for reducing test power and test application time and it is demonstrated that, about 2/spl times/ shift time and 20/ spl times/ test power reduction can be achieved.
Abstract: Conventional serial connection of internal scan chains brings the power and time penalty. A parallel core wrapper design (pCWD) approach is presented in this paper for reducing test power and test application time. The pCWD utilizes overlapping scan slices to reduce the number of scan slices loading. Experimental results on d695 of ITC2002 benchmark demonstrated that, about 2/spl times/ shift time and 20/spl times/ test power reduction can be achieved.
2 citations
15 Nov 2004
TL;DR: Experimental results for two ITC '02 SOC benchmarks show that the pair balance-based test scheduling technique achieves less test time compared to the previous approaches.
Abstract: Along with more pre-designed and pre-verified cores are integrated into a single chip to construct an entire system, the test application time increases significantly. This paper presents a novel test scheduling solution, unlike previous techniques that take advantage of balanced scan chains of every single core, utilizing the balance of pairwise combined cores. Experimental results for two ITC '02 SOC benchmarks show that the pair balance-based test scheduling technique achieves less test time compared to the previous approaches.
2 citations
27 Jun 2004
TL;DR: An integrated system for VLSI/ULSI physical design is implemented that is integrated in three different layers, which are called the data interface layer, the data management layer (DML), and the data display layer (DDL).
Abstract: The paper studies and implements an integrated system for VLSI/ULSI physical design. A hierarchy mechanism is used to get great efficiency and speedup. The physical design system is integrated in three different layers, which are called the data interface layer (DIL), the data management layer (DML) and the data display layer (DDL). A quadtree data structure is used in DDL to accelerate the graphics showing and the interaction between users and the system.
1 citations