In the recent shift to the multi-core and many-core era, where systems tend to be heterogeneous even at chip level, SIMD instruction sets and accelerators that exploit parallelism in a similar way are coming into prominence in new multiprocessors and systems. This heterogeneity, even at chip level, is causing a lot of trouble to compilers and parallel programming models in terms of being able to maximize the profitability of the computational resources in an easy, generic, efficient and portable fashion.
Although a lot of work on automatic vectorization/simdization techniques has been done over the years, compilers show important limitations when vectorizing code with pointers and function calls because of the traditional compiler analysis limitations, such as those in pointers aliasing analysis.
Concerning parallel programming models, some of them are restricted to specific architectures while other portable ones, such as OpenCL, require programmers to face low-level architecture details and hard source code transformations, presenting important performance problems among different architectures, which requires new tuning efforts.
In an attempt to offer a unified and generic solution to the auto-vectorization/simdization and portability problems, we propose User-directed Vectorization in OmpSs, a high-level programming model extension that offers developers the possibility to easily guide the compiler in the vectorization process just introducing some simple notations on the vectorizable areas of the code, such loops and functions.
We focused our particular design, implementation and evaluation on the Intel SSE instruction set for CPUs, getting the same or higher speed-ups than using the GCC compiler auto-vectorization in easily-vectorizable codes, and a performance improvement of up to 2.30 in more complex codes where GCC is not able to apply auto-vectorization and the hand-coded OpenCL version reaches a speed-up of 2.23.

https://upcommons.upc.edu/bitstream/handle/2099.1/25812/Master%20Tesis%20-%20Diego%20Caballero.pdf;sequence=1

User-directed Vectorization in OmpSs

Thread level speculation (TLS) and Transactional memory (TM) are both promising way to enhance the performance of chip multiprocessor (CMP). The complexity of providing efficient memory accesses buffering mechanism in TLS can be supported by TM logically. This paper proposes a speculative multi-threading model based on transactional memory, including its special hardware, compiler and execution support. It's a low-design-complexity approach to effective unified support for both TLS&TM. The experimental results show that our framework is competent to exploit the speculative thread-level parallelism with little parallel degree loss by the parallel & ordered transaction partition strategy.

Yuan Liu

Papers

Exploiting Speculative Thread-Level Parallelism Based on Transactional Memory