In this paper, improved algorithms for radix-4 and radix-8 FFT are presented. This is achieved by re-indexing a subset of the output samples resulting from the conventional decompositions in the radix-4 and radix-8 FFT algorithms. These modified radix-4 and radix-8 algorithms provide savings of more than 33% and 42% respectively in the number of twiddle factor evaluations or accesses to the lookup table compared to the corresponding conventional FFT algorithms without imposing any additional complexity.

Improved radix-4 and radix-8 FFT algorithms

Optimizing the number of arithmetic operations required in fast Fourier transform (FFT) algorithms has been the focus of extensive research, but memory management is of comparable importance on modern processors. In this article, we investigate two known FFT algorithms, G and GT , that are similar to Cooley-Tukey decimation-in-time and decimation-in-frequency FFT algorithms but that give an asymptotic reduction in the number of twiddle factor loads required for depth-first recursions. The algorithms also allow for aggressive vectorization (even for non-power-of-2 orders) and easier optimization of trivial twiddle factor multiplies. We benchmark G and GT implementations with comparable Cooley-Tukey implementations on commodity hardware. In a comparison designed to isolate the effect of twiddle factor access optimization, these benchmarks show typical speedups ranging from 10% to 65%, depending on transform order, precision, and vectorization. A more heavily optimized implementation of GT yields substantial performance improvements over the widely used code FFTW for many transform orders. The twiddle factor access optimization technique can be generalized to other common FFT algorithms, including real-data FFTs, split-radix FFTs, and multidimensional FFTs.

Improved Twiddle Access for Fast Fourier Transforms

This paper presents a high performance FFT ASIP. The resulting programmable solution is scalable for the order of the FFT and capable of satisfying performance requirements of various OFDM wireless standards. The IEEE 802.15.3a ultra wideband OFDM - being the most time critical of these standards because of the computation of a 128-point FFT within 312.5 ns - has been the primary performance target of the scalable ASIP. The resulting ASIP adopts a vectorial ultra-long instruction word (ULIW) approach. The design decisions are evaluated with regards to processing speed, area and power dissipation.

A multistandard FFT processor for wireless system-on-chip implementations

Several SOA (state of the art) self-tuning software libraries exist, such as the Fastest Fourier Transform in the West (FFTW) for fast Fourier transform (FFT). FFT is a highly important kernel and the performance of its software implementations depends on the memory hierarchy's utilization. FFTW minimizes register spills and data cache accesses by finding a schedule that is independent of the number of the registers and of the number of levels and size of the cache, which is a serious drawback. In this paper, a new methodology is presented, achieving improved performance by focusing on memory hierarchy utilization. The proposed methodology has three major advantages. First, the combination of production and consumption of butterflies' results, data reuse, FFT parallelism, symmetries of twiddle factors and also additions by zeros and multiplications by zeros and ones when twiddle factors are zero or one, are fully and simultaneously exploited. Second, the optimal solution is found according to the number of the registers, the data cache sizes, the number of the levels of data cache hierarchy, the main memory page size, the associativity of the data caches and the data cache line sizes, which are also considered simultaneously and not separate. Third, compilation time and source code size are very small compared with FFTW. The proposed methodology achieves performance gain about 40% (speed-up of 1.7) for architectures with small data cache sizes where memory management has a larger effect on performance and 20% (speed-up of 1.25) on average for architectures with large data cache sizes (Pentium) in comparison with FFTW.

A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization

An improved radix-16 decimation-in-frequency (DIF) FFT algorithm is proposed by introducing new indices for some of the output sub-sequences resulting from the conventional radix-16 DIF decomposition of the DFT. This improved radix-16 DIF FFT algorithm achieves savings of more than 46% in the number of twiddle factor evaluations or accesses to the lookup table and address generations compared to the conventional radix-16 DIF FFT algorithm. These savings are achieved without imposing any additional computational or structural complexity in the algorithm.

An improved radix-16 FFT algorithm

In microprocessor-based systems, memory access is expensive due to longer latency and higher power consumption. In this paper, we present a novel FFT algorithm to reduce the frequency of memory access as well as multiplication operations. For an N-point FFT, we design the FFT with two distinct sections: (1) The first section of the FFT structure computes the butterflies involving twiddle factors WNj (j ≠ 0) through a computation/partitioning scheme similar to the Hoffman coding. In this section, all the butterflies sharing the same twiddle factor will be clustered and computed together. In this way, redundant memory access to load twiddle factors is avoided. (2) In the second section, the remaining (N - 1) butterflies involving the twiddle factor WN0 are computed with a register-based breadth first tree traversal algorithm. This novel twiddle factor-based FFT is tested on the TIT MS320C62x digital signal processor. The results show that, for a 32-point FFT, the new algorithm leads to as much as 20% reduction in clock cycles and an average of 30% reduction in memory access than that of the conventional DIF FFT.

Yuke Wang

Papers

Twiddle-factor-based FFT algorithm with reduced memory access