This paper introduces a methodology to co-design on-chip linear dropout regulator (LDO) with power distribution network of package and PCB board based on Laplace transform method. A practical methodology demonstrates the effectiveness and the efficiency of the Laplace model in the time domain and is derived that takes into account LDO-PDN system impedance response. LDO pass transistor size and output decoupling capacitor optimization flow is proposed to meet the system voltage noise requirements. The goal is to provide sufficient performance for efficient system solutions in the early stages of design and achieve success at the system level.

Power Distribution Network Optimization for On-Die Regulator with Laplace Transform Technique

A semiconductor device may include a plurality of memory banks and an output buffer that couples to the plurality of memory banks. The output buffer may produce a data voltage signal representative of data to be read from at least one of the plurality of memory banks. The semiconductor device may also include a driver circuit having a pulse generator and a pull-down switch that couples the output buffer to ground, such that the pull-down switch provides the data voltage signal to the output buffer. The semiconductor device may also include a test mode circuit that determines whether the data voltage signal is acceptable and sends an enable signal to the pulse generator in response to the data voltage signal not being acceptable. The enable signal causes the pulse generator to effectively operate with variations in processing, temperature, and voltage properties associated with testing.

Systems and methods for conserving power in signal quality operations for memory devices

In this paper, we present a novel power integrity simulation method based on Markov-Chain-based Stochastic Random Power Model (MCSRPM). In this method, we analyze numerous memory traffic cases of an actual system, create a Markov-Chain table which can reflect in system memory scheduling, and create MCSRPM by applying it to DDR5 DRAM state diagram. In practice, we have successfully verified that MCSRPM can predict power noise measured on a DDR5 server system. Also, it is possible to verify many power scenarios predictable in DDR5 systems at once, and confirmed that the analysis time has reduced by more than 60% compared to CPM-based simulation which can only verify few power scenarios. 

A Novel Simulation Methodology Reflecting System Power Scenario using a Markov-Chain-based Stochastic Random Power Model

A memory module includes a circuit board, a plurality of memory devices, and a power management integrated circuit (PMIC). The circuit board includes first connectors, a second connector, and a third connector connected to an external device. The plurality of memory devices are mounted on the circuit board, and connected to the first connectors. The PMIC receives a first voltage through the second connector, generates a second voltage using the first voltage, and provides the second voltage to the plurality of memory devices The PMIC adjusts the second voltage based on a signal received through the third connector such that a voltage difference of the first voltage and the second voltage is reduced in a training mode of the memory module.

Memory modules and memory systems including a power management integrated circuit

A memory device includes a plurality of memory chips for writing and reading data in response to a control command and an address signal, and a control logic circuit for transferring the control command and the address signal to the plurality of the memory chips, and receiving a first command from a memory controller to perform a first operation, different from a refresh operation, on at least one of a plurality of the memory chips. The control logic circuit, in response to a refresh command, transmits the first command to at least one of a plurality of the memory chips and performs the first operation during a pre-determined refresh time interval without carrying out the refresh operation.

Memory device and memory system comprising the same

With the ever-increasing demand for both highperformance and low-power memory modules, it is becoming more and more difficult to meet the SI/PI-related target specifications. This problem can be further aggravated as the supply voltage of Double Data Rate (DDR) memory module decreases from 1.2 V down to 1.1 V for DDR5, possibly resulting in more logic malfunctions of the system. In order to mitigate these problems, Power Management Integrated Circuit (PMIC) is adopted on the DDR5 module to enhance the PI performance. Accordingly, an accurate evaluation of its characteristics has become of utmost importance for prediction of module-level voltage ripple (AC) and IR drop (DC) characteristics. In this paper, a novel methodology for accurate analysis of module-level PI performance, which includes non-linear PMIC characteristics along with other power models of passive components and CPM, is proposed. Through a series of simulations in both time and frequency domains, we successfully verified the accuracy of the proposed methodology and proved its high practicality.

A Novel Dynamic PI Simulation Methodology Including Non-linear PMIC Characteristics for DDR5 Module

A memory module includes semiconductor memory devices, a power management integrated circuit (PMIC), and a control device. The semiconductor memory devices, mounted on a circuit board, operate based on a power supply voltage. The PMIC, mounted on the circuit board, generates the power supply voltage, provides the power supply voltage to the semiconductor memory devices, and stores a trimming control code associated with a minimum level of the power supply voltage when the semiconductor memory devices operate normally in a test mode. During the test mode, the PMIC adjusts a level of the power supply voltage, tests the semiconductor memory devices using the adjusted power supply voltage, and stores the trimming control code based on a result of the test. The control device controls the PMIC based on a first control signal received from an external device.

Memory modules, methods of operating the memory modules, and test systems of the memory modules

Memory modules storing a trimming control code associated with a minimum level of a power supply voltage, methods of operating the memory modules, and test systems of the memory modules

Yun Jin-Seong

Papers

A Novel Dynamic PI Simulation Methodology Including Non-linear PMIC Characteristics for DDR5 Module

Memory modules, methods of operating the memory modules, and test systems of the memory modules

Memory modules storing a trimming control code associated with a minimum level of a power supply voltage, methods of operating the memory modules, and test systems of the memory modules

Memory modules and memory systems including the same

Memory modules and memory systems including a power management integrated circuit