An improved successive-approximation type ADC that uses both charge-scaled and voltage scaled approximation. The present invention provides a high noise immunity, high speed ADC using a differential voltage scaled DAC. The differential voltage scaled output scheme of the present invention advantageously applies voltage scaling to a capacitor on both inputs to the comparator. The dual voltage scaling is preferably done by connecting two switches to each tap on the bottom half of a resistor string, and no switches to the top half of the resistor string, using one set of tap switches for adjusting a charge on capacitor on the first input of the comparator and the second set of tap switches for adjusting a charge on capacitor on the second input of the comparator.

Analog to digital converter with a differential output resistor-digital-to-analog-converter for improved noise reduction

A successive approximation register analog-to-digital converter (SAR ADC) having a sample, hold and convert amplifier circuit may be configured for either a single channel SAR ADC or a multiple channel SAR ADC. Switches or metal connection options, e.g., bit configurable or metal mask configurable, respectively, may be used to configure a common capacitor area, a portion of which may be used as a reconfigurable charge-redistribution digital-to-analog converter (CDAC) of the SAR ADC as either a single channel sample, hold and convert 12-bit capacitor configuration or a four channel sample, hold and convert 10-bit capacitor configuration. All other parts of the SAR ADC circuitry may be substantially the same for either configuration, e.g., the resistive digital-to-analog converter (RDAC), successive approximation register (SAR), ADC controller, sample, hold and convert switches, comparator, etc, may be substantially the same for either the single or multiple channel SAR ADC configurations.

Analog-to-digital converter with interchangeable resolution and sample and hold amplifier channels

A switched-capacitor digital-to-analog converter circuit is disclosed. The switched-capacitor digital-to-analog converter circuit includes crossing switches for each capacitor branch, the crossing switches are used to eliminate cross interference between digital-to-analog converter blocks sharing the same reference voltages.

Code independent charge transfer scheme for switched-capacitor digital-to-analog converter

When a clock φ1 is in high state, based on a digital signal, capacitive elements C11 to C1 i are connected between a reference voltage Vr+ or Vr− and a sampling ground V1 to hold a charge corresponding to difference between the reference voltage and sampling ground V1 while capacitive elements C21 to C2 i are connected between a reference voltage Vr+ or Vr− and a sampling ground V2 to hold a charge corresponding to difference between the reference voltage and sampling ground V2. When a clock φ2 is in high state, the capacitive elements C11 to C1 i and C21 to C2 i are connected, in parallel with a feedback capacitive element Cfb, between an input terminal and output terminal of an operational amplifier 100. To obtain a D/A converter which operates at a lower supply voltage and produces output signals low in harmonic components and noise components.

D/A converter and delta-sigma D/A converter

A device ( 200, FIG. 2 ) includes receive hardware ( 204 ) which performs analog-to-digital conversion. In accordance with an embodiment of the invention, the receive hardware includes a pipelined analog-to-digital converter ( 320, FIG. 3 ). Sample-and-hold circuitry ( 410, FIG. 4 ) associated with the analog-to-digital converter is configured (FIGS. 8 , and 12 - 14 ) and switched (FIG. 7 ) in a manner that provides intermediate frequency to baseband downconversion and skew-insensitive double-sampling.

Double-sampled, sample-and-hold circuit with downconversion

In a D/A converter employed in audio systems and various communicating equipment, particularly for using a digital 1-bit data stream as an input and an analog signal as an output, a switched capacitor digital-analog converter having a decreased harmonic distortion utilizes a charge subtraction method in a low-pass filter instead of employing a bypass filter to prevent an operational amplifier from deviating from a linear range due to a switching noise. The bypass capacitor heretofore used in the D/A converter is not employed to shrink the chip designing area.

Yun Tae Shin

Papers

Switched capacitor digital-analog converter with a decreased harmonic distortion