A wireless communication device configured for receiving a wireless multiple-input and multiple-output signal. The wireless communication device includes a first multiple-input and multiple-output carrier aggregation receiver reuse architecture. The first multiple-input and multiple-output carrier aggregation receiver reuse architecture includes a first antenna, a second antenna and a transceiver chip. The first multiple-input and multiple-output carrier aggregation receiver reuse architecture reuses a first carrier aggregation receiver path. The wireless communication device also includes a second multiple-input and multiple-output carrier aggregation receiver reuse architecture. The second multiple-input and multiple-output carrier aggregation receiver reuse architecture includes a third antenna, a fourth antenna and a receiver chip. The second multiple-input and multiple-output carrier aggregation receiver reuse architecture reuses a second carrier aggregation receiver path.

Multiple-input and multiple-output carrier aggregation receiver reuse architecture

Low noise amplifiers (LNAs) supporting carrier aggregation are disclosed. In an exemplary design, an apparatus includes first and second amplifier stages, e.g., for a carrier aggregation (CA) LNA or a multiple-input multiple-output (MIMO) LNA. The first amplifier stage receives and amplifies an input radio frequency (RF) signal and provides a first output RF signal to a first load circuit when the first amplifier stage is enabled. The input RF signal includes transmissions sent on multiple carriers at different frequencies to a wireless device. The second amplifier stage receives and amplifies the input RF signal and provides a second output RF signal to a second load circuit when the second amplifier stage is enabled. Each amplifier stage may include a gain transistor coupled to a cascode transistor.

Low noise amplifiers for carrier aggregation

A wireless communication device configured for receiving a multiple carrier signal is described. The wireless communication device includes a primary signal splitting carrier aggregation architecture. The primary signal splitting carrier aggregation architecture includes a primary antenna and a transceiver chip. The primary signal splitting carrier aggregation architecture reuses a first diversity/simultaneous hybrid dual receiver path. The wireless communication device also includes a secondary signal splitting carrier aggregation architecture. The secondary signal splitting carrier aggregation architecture includes a secondary antenna and a receiver chip. The secondary signal splitting carrier aggregation architecture reuses a second diversity/simultaneous hybrid dual receiver path.

Signal splitting carrier aggregation receiver architecture

A receiver architecture for carrier aggregation is disclosed. In an exemplary design, an apparatus (e.g., a wireless device, a circuit module, etc.) includes a plurality of low noise amplifiers (LNAs), a plurality of switches, and at least one downconverter. The LNAs receive and amplify at least one input radio frequency (RF) signal and provide at least one amplified RF signal. The switches are coupled to the outputs of the plurality of LNAs. The at least one downconverter is coupled to the plurality of switches, downconverts the at least one amplified RF signal, and provides at least one downconverted signal. The switches reduce the number of downconverters needed to support reception of transmissions on multiple sets of carriers via multiple receive antennas. The LNAs and the switches may be implemented on at least one front-end module or a back-end module. The downconverter(s) are implemented on the back-end module.

Carrier aggregation receiver architecture

A wireless communication device configured for receiving a multiple carrier signal is described. The wireless communication device includes a single-chip signal splitting carrier aggregation receiver architecture. The single-chip signal splitting carrier aggregation receiver architecture includes a primary antenna, a secondary antenna and a transceiver chip. The single-chip signal splitting carrier aggregation receiver architecture reuses a simultaneous hybrid dual receiver path.

Single-chip signal splitting carrier aggregation receiver architecture

Provided are a receiving circuit including a balun circuit and a notch filter, and an operating method thereof. The receiving circuit includes a transformer, a notch filter, and a mixer. The transformer converts a single input signal to a differential input signal using a first tap. The notch filter blocks a specific frequency band of the single input signal by connecting a second tap with the first tap of the transformer using a condenser.

Receiving circuit including balun circuit and notch filter and operating method thereof

An apparatus and method for frequency synthesis using a Delay Locked Loop (DLL) are provided. The apparatus includes the DLL, an edge pulse generator, and an inductive-capacitive (LC) tank switch. If phases of a reference frequency signal and a feedback signal are the same and thus are locked, the DLL delays the reference frequency signal. The edge pulse generator generates a plurality of pulse signals representing phase delay amounts of signals. The LC tank switch combines the plurality of pulse signals and generates frequency.

Apparatus and method for frequency synthesis using delay locked loop

An apparatus and a method for calibrating a Voltage Controlled Oscillator (VCO) using a fast frequency comparison based on phase manipulation are provided. The calibrating apparatus includes a phase shifter for comparing an input reference frequency and an input divided frequency and shifting a phase of the reference frequency to make the phase of the reference frequency align with a phase of the divided frequency; a frequency comparator for determining which one of the phase-shifted reference frequency and the divided frequency is higher; and a cap-bank control for determining a frequency to use based on a comparison result of the frequency comparator.

Apparatus and method for vco calibration using fast frequency comparison based on phase manipluation

PURPOSE: A receiving circuit including a balun circuit and a notch filter and an operating method thereof are provided to reduce the number of external parts and simplify an interface circuit. CONSTITUTION: A transformer converts a single input signal to a differential input signal by using the first tab. A condenser is connected between the first and second taps of a transformer. A notch filter(140) blocks a specific frequency band of the single input signal. A low noise amplifier low-noise-amplifies the signal received through an antenna. The low noise amplifier outputs the amplified signal to an input terminal of the transformer.

Yun-Young Choi

Papers

Receiving circuit including balun circuit and notch filter and operating method thereof

Apparatus and method for frequency synthesis using delay locked loop

Apparatus and method for vco calibration using fast frequency comparison based on phase manipluation

Receive circuit and method for operating balun circuit and notch filter