In this paper, a low-complexity adaptive edge-enhanced algorithm is proposed for the implementation of 2-D image scaling applications. The proposed novel algorithm consists of a linear space-variant edge detector, a low complexity sharpening spatial filter, and a simplified bilinear interpolation. The edge detector is designed to discover the image edges by a low-cost edge-catching technique. The sharpening spatial filter is added as a prefilter to reduce the blurring effect produced by the bilinear interpolation. Furthermore, an adaptive technology is used to enhance the effect of the edge detector by adaptively selecting the input pixels of the bilinear interpolation. In addition, an algebraic manipulation and a hardware sharing techniques are used to simplify bilinear interpolation, which efficiently reduces the computing resources and silicon area in very large scale integration (VLSI) circuits. By adding eight 8-bit registers as a register bank, this design can process streaming data directly and requires only a one-line-buffer memory. The VLSI architecture of this paper contains 6.67-K gate counts and achieves about 280-MHz processing rate by using the TSMC 0.13-um CMOS process. Compared with previous low-complexity techniques, this paper performs with better quality, higher performance, less memory requirements, and lower hardware cost than other image scaling methods.

VLSI Implementation of an Adaptive Edge-Enhanced Image Scalar for Real-Time Multimedia Applications

Image interpolation is the process of calculating the unknown pixel values from known pixel values. This procedure can be used for enlarging as well as contrasting digital image. Image interpolation techniques are used for various applications such as consumer electronics, medical imaging and digital radiograph. There are various algorithms are available for image scaling. These techniques are mainly divided into two types such as adaptive and non-adaptive image interpolation. These two interpolation techniques are further divided into various types. In this paper, these different adaptive and non-adaptive image interpolation techniques are overviewed and compared on the basis of their performance parameter i.e PSNR (Peak Signal-to-Noise Ratio). From the various interpolation techniques, adaptive edge enhanced technique gives better PSNR of 38.95dB.

Adaptive and Non-adaptive Image Interpolation Techniques

Super-resolution imaging (S.R.) is a series of techniques that enhance the resolution of an imaging system, especially in surveillance cameras where simplicity and low cost are of great importance. S.R. image reconstruction can be viewed as a three-stage process: image interpolation, image registration, and fusion. Image interpolation is one of the most critical steps in the S.R. algorithms and has a significant influence on the quality of the output image. In this paper, two hardware-efficient interpolation methods are proposed for these platforms, mainly for the mobile application. Experiments and results on the synthetic and real image sequences clearly validate the performance of the proposed scheme. They indicate that the proposed approach is practically applicable to real-world applications. The algorithms are implemented in a Field Programmable Gate Array (FPGA) device using a pipelined architecture. The implementation results show the advantages of the proposed methods regarding area, performance, and output quality.

Low-Cost Implementation of Bilinear and Bicubic Image Interpolation for Real-Time Image Super-Resolution.

An accurate, hardware efficient and fast image rescaling unit is a crucial part of any real-time image processing system. Although there are a number of image scaling algorithms existing in the literature but Bicubic and Bilinear interpolation algorithms are most widely used. In the recent years, numerous algorithms have been proposed that aim to bridge the gap between these two standard algorithms, by attempting to provide high image quality of the former while maintaining the computational simplicity of the latter. This paper proposes a novel image resizing algorithm which uses a four-part piecewise linear function that closely mimics the behavior of the bicubic kernel, and thus provides high quality resized images comparable to Bicubic interpolation while having a much lower computational cost. An optimized architecture is proposed to implement this algorithm which features a high re-use of hardware units for coefficient generation so that the hardware cost is comparable to that of bilinear interpolation. The architecture and algorithm have been designed in tandem so as to meet the real-time requirements of applications such as automated video surveillance, requiring minimal hardware use without compromising on image quality.

Hardware accelerator for real-time image resizing

Super-resolution imaging (SR) is a series of techniques that enhance the resolution of an imaging system, especially in surveillance cameras where simplicity and low cost are of great importance SR image reconstruction can be viewed as a three-stage process: image interpolation, image registration, and fusion Image interpolation is one of the most critical steps in the SR algorithms and has a significant influence on the quality of the output image In this paper, two hardware-efficient interpolation methods are proposed for these platforms, mainly for the mobile application Experiments and results on the synthetic and real image sequences clearly validate the performance of the proposed scheme They indicate that the proposed approach is practically applicable to real-world applications The algorithms are implemented in a Field Programmable Gate Array (FPGA) device using a pipelined architecture The implementation results show the advantages of the proposed methods regarding area, performance, and output quality

Low-Cost Implementation of Bilinear and Bicubic Image Interpolation for Real-Time Image Super-Resolution

There is an improvement to the Bicubic interpolation enlargement algorithm based on the hardware parallel processing in this article. Search table method used in this paper has avoided massive cubic and the floating numbers multiply operation. It reduces the computation load greatly. Convolution operation in tow directions, level and vertical, of the 4x4 picture element matrix on FPGA has been realized by LPM. The Bicubic interpolation enlargement algorithm is completely based on the hardware parallel characteristic to realize. This method has the superiority in the computation speed and occupies on the resources.

Yunshan Zhang

Papers

The Hardware Realization of the Bicubic Interpolation Enlargement Algorithm Based on FPGA