An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

In fabricating a thin film transistor, an active layer comprising a silicon semiconductor is formed on a substrate having an insulating surface Hydrogen is introduced into The active layer A thin film comprising SiO x N y is formed to cover the active layer and then a gate insulating film comprising a silicon oxide film formed on the thin film comprising SiO x N y  Also, a thin film comprising SiO x N y is formed under the active layer The active layer includes a metal element at a concentration of 1×10 15 to 1×10 19 cm −3 and hydrogen at a concentration of 2×10 19 to 5×10 21 cm −3 

Semiconductor device and method for forming the same

An electro-optical device having a plurality of pixels including a plurality of EL elements, wherein the electro-optical device provides a gray scale display by controlling a period of time at which the plurality of the EL elements emit light in one frame period; the plurality of the EL elements have a first electrode and a second electrode; the first electrode is held at a constant potential; and a potential of the second electrode changes in such a manner that a polarity of an EL driving voltage, which is a difference between the potentials applied to the first and second electrodes, is inverted for each one frame period.

Electro-optical device

One of the fundamental problems in the continued scaling of transistors is the 60 mV/dec room temperature limit in the subthreshold slope. In part I this work, a novel transistor based on the field-effect control of impact-ionization (I-MOS) is explored through detailed device and circuit simulations. The I-MOS uses gated-modulation of the breakdown voltage of a p-i-n diode to switch from the OFF state to the ON state and vice-versa. Device simulations using MEDICI show that the I-MOS has a subthreshold slope of 5 mV/dec or lower and I/sub ON/>1 mA//spl mu/m at 400 K. Simulations were used to further explore the characteristics of the I-MOS including the transients of the turn-on mechanism, the short-channel effect, scalability, and other important device attributes. Circuit mode simulations were also used to explore circuit design using I-MOS devices and the design of an I-MOS inverter. These simulations indicated that the I-MOS has the potential to replace CMOS in high performance and low power digital applications. Part II of this work focuses on I-MOS experimental results with emphasis on hot carrier effects, germanium p-i-n data and breakdown in recessed structure devices.

Impact ionization MOS (I-MOS)-Part I: device and circuit simulations

Silicon-on-insulator (SOI) n-channel transistors have been made in thin (90 nm) silicon films Both modeling and experimental results show that excellent subthreshold slopes can be obtained (62 mV/ decade) when the silicon film thickness is smaller than the maximum depletion depth in the transistor channel For comparison, the subthreshold slope of transistors made in thicker films is also reported

Subthreshold slope of thin-film SOI MOSFET's

Diffusion Selfaligned MOST; A New Approach for High Speed Device

The ideal low- and high-frequency capacitance-voltage curves of a semiconductor(2)-insulator-semiconductor(1) (SIS) structure were first calculated with the insulator thickness, conductivity types and doping concentrations in semiconductor(1) and semiconductor(2) as parameters. The effects of fixed oxide charge and interface trap charge on the low and high frequency capacitance-voltage curves were also calculated. It was found that the fixed oxide sheet charge density with its centroid and the order estimation of the interface trap charge density with its effective type in addition to the insulator thickness, conductivity types and doping concentrations in semiconductor(1) and semiconductor(2) could be estimated from measured low and high frequency capacitance-voltage curves of an SIS structure.

Capacitance-voltage characteristics of Semiconductor-Insulator-Semiconductor (SIS) structure

Experimental fabrication of an XMOS transistor which has two insulated gates called upper-gate and lower-gate has been performed using lateral solid-phase epitaxy of a-Si film deposited by CVD of SiH4. The fabricated XMOS transistors exhibited no punch-through effect and good controllability of the upper-gate threshold voltage by the voltage applied to the lower-gate. It was found that the measured values of the slopes on the upper-gate threshold voltage control by the lower-gate voltage showed good agreement with the calculated value of the slope derived from a simple capacitance couple model.

Experimental Fabrication of XMOS Transistors Using Lateral Solid-Phase Epitaxy of CVD Silicon Films

A simple method to produce an avalanche breakdown with a constant avalanche current in the silicon substrate of a MOS diode and to inject hot carriers into the gate oxide is presented. The shift of flatband voltage and that of the breakdown voltage of an n-type MOS diode are observed by hole injection into the gate oxide grown in dry oxygen using the above method. It is observed that about 1/10 of the injected holes could be captured by traps in the gate oxide. It is indicated by both the bias-temperature treatment and the avalanche injection process that hole traps would be generated by avalanche injected holes in the gate oxide. The trapped holes are located near the Si–SiO2 interface decaying from that interface.

https://iopscience.iop.org/article/10.1143/JJAP.14.1539/pdf

Carrier Injection into SiO2 from Si Surface Driven to Avalanche Breakdown by a Linear Ramp Pulse, and Trapping, Distribution and Thermal Annealing of Injected Holes in SiO2

Threshold voltage (Vth) controllability of diffusion self-aligned (DSA) MOS FET fabricated by a full ion implantation and N2 drive-in technique has been examined and analyzed As the p-type diffused region (base) and the n-type diffused region (source) were formed by this method, the impurity profiles of these layers became reproducible and Vth controllability were improved as compared with the usual thermal predeposition process A simplified Vth model showed a good agreement with the experimental results The performance of DSA ED MOS IC has been also discussed In the 19 stage ring oscillators, the propagation delay time per unit gate was 036 ns (Vdd=80 V) for high speed design and the power-delay product was 0055 pJ (Vdd=27 V) for low power design A 1024-bits random access memory has been developed on the basis of above mentioned results, and the access time of 50 ns has been obtained

Yutaka Hayashi

Papers

Diffusion Selfaligned MOST; A New Approach for High Speed Device

Capacitance-voltage characteristics of Semiconductor-Insulator-Semiconductor (SIS) structure

Experimental Fabrication of XMOS Transistors Using Lateral Solid-Phase Epitaxy of CVD Silicon Films

Carrier Injection into SiO2 from Si Surface Driven to Avalanche Breakdown by a Linear Ramp Pulse, and Trapping, Distribution and Thermal Annealing of Injected Holes in SiO2

Fully Ion Implanted DSA MOS IC