Multirate (decimation/interpolation) filters are among the essential signal processing components in space-borne instruments where Finite Impulse Response (FIR) filters are often used to minimize nonlinear group delay and finite-precision effects. Cascaded (multi-stage) designs of Multi-Rate FIR (MRFIR) filters are further used for large rate change ratio, in order to lower the required throughput while simultaneously achieving comparable or better performance than single-stage designs. Traditional representation and implementation of MRFIR employ polyphase decomposition of the original filter structure, whose main purpose is to compute only the needed output at the lowest possible sampling rate. In this paper, an alternative representation and implementation technique, called TD-MRFIR (Thread Decomposition MRFIR), is presented. The basic idea is to decompose MRFIR into output computational threads, in contrast to a structural decomposition of the original filter as done in the polyphase decomposition. Each thread represents an instance of the finite convolution required to produce a single output of the MRFIR. The filter is thus viewed as a finite collection of concurrent threads. The technical details of TD-MRFIR will be explained, first showing its applicability to the implementation of downsampling, upsampling, and resampling FIR filters, and then describing a general strategy to optimally allocate the number of filter taps. A particular FPGA design of multi-stage TD-MRFIR for the L-band radar of NASA's SMAP (Soil Moisture Active Passive) instrument is demonstrated; and its implementation results in several targeted FPGA devices are summarized in terms of the functional (bit width, fixed-point error) and performance (time closure, resource usage, and power estimation) parameters.

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Optimized FPGA implementation of Multi-Rate FIR filters through Thread Decomposition

iBoard is a highly capable, highly reusable, and modular FPGA-based common building block for instrument digital electronics. It is targeted to those space-borne instruments that require high-performance on-board processing capabilities. The paper explains the design methodology, describes requirements of flight instrument digital electronics, presents implementation of the first prototype, iBoard 2.

iBoard: A highly-capable, high-performance, reconfigurable FPGA-based building block for flight instrument digital electronics

In this paper proposed is a cost-efficient architecture of FIR filter for portable digital spectrum analyzers. In order to reduce the hardware complexity, we split an FIR filter into multiple stages, which share the hardware resources such as multipliers and adders with one another. It makes sense because portable spectrum analyzers should be implemented with very low hardware costs and the real-time working is not mandatory in the systems. The proposed architecture can reduce the hardware costs to a quarter of existing FIR filter's complexity.

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Multi-stage FIR filter design for portable digital spectrum analyzers

The NASA-ISRO Synthetic Aperture Radar (NISAR) L-band SAR instrument employs multiple digital channels to optimize resolution while keeping a large swath on a single pass. High-speed digitization with fine synchronization and digital beam forming are necessary in order to facilitate this new technique called SweepSAR. An architecture employing multiple FPGA based digital signal processors has been conceived to facilitate digital calibration on an individual channel basis as well as digital signal processing to optimize the receive signal. On-board processing and data compression has been implemented to reduce the volume of data in order to satisfy the operational requirements of near global coverage for the desired science targets. A novel command and timing architecture was developed to manage this complex system to meet the challenging project requirements. The NISAR L-band Digital Electronics Subsystem is the combination of the hardware, firmware and software components architected and implemented to operate this radar and return the desired quantity and quality of data for the science community.

NISAR L-band digital electronics subsystem: A multichannel system with distributed processors for digital beam forming and mode dependent filtering

JPL has developed a small(<5 kg) spacecraft capable of visual inspection of a host vehicle with support from NASA's Exploration Systems Mission Directorate (ESMD). This paper describes the multi-mission utility of the Micro-Inspector and presents an overview of the spacecraft system and subsystem designs, description of a typical inspection mission scenario, and initial hardware demonstrations of key subsystems, partially integrated with each other in a Micro-Inspector testbed at JPL.

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Micro-Inspector Spacecraft: An Overview

ISAAC is a highly capable, highly reusable, modular, and integrated FPGA-based common instrument control and computing platform for a wide range of instrument needs as defined in the Earth Science National Research Council (NRC) Decadal Survey Report. This paper presents its motivation, technical approach, and the infrastructure elements. It also describes the first prototype, ISAAC I, and its application in the design of SMAP L-band radar digital filter.

ISAAC - a case of highly-reusable, highly-capable computing and control platform for radar applications

This paper describes development of a radiation tolerant, low power, reconfigurable avionics module aimed at meeting the avionics needs of the JPL Micro-Inspector spacecraft. This module represents a complete avionics system, consisting of two PowerPC 405 CPUs embedded within a reconfigurable FPGA fabric of over 8 Million logic gates, 64MB of EDAC protected Flash storage and 128MB of EDAC protected DDR SDRAM or SDRAM memories, along with FPGA SEU mitigation logic, and all necessary power conversion. Processor SEU mitigation is achieved by running the two processors in a lock-step and compare configuration. All of these building blocks are integrated into a double sided circuit board that takes as little as 6 square inches of board space. This module can be embedded into a user system as part of a bigger circuit assembly or as a self contained module. This module is being developed as part of a JPL led Micro-Inspector Program, funded by NASA ESMD aimed at producing a 10Kg micro spacecraft.

Micro-Inspector Avionics Module (MAM): A Self-Contained Low Power, Reconfigurable Avionics Platform for Small Spacecrafts and Instruments

Historically, computationally-intensive data processing for space-borne instruments has heavily relied on ground-based computing resources. But with recent advances in functional densities of Field-Programmable Gate-Arrays (FPGAs), there has been an increasing desire to shift more processing on-board; therefore relaxing the downlink data bandwidth requirements. Fast Fourier Transforms (FFTs) are commonly-used building blocks for data processing applications, with a growing need to increase the FFT block size. Many existing FFT architectures have mainly emphasized on low power consumption or resource usage; but as the block size of the FFT grows, the throughput is often compromised first. In addition to power and resource constraints, space-borne digital systems are also limited to a small set of space-qualified memory elements, which typically lag behind the commercially available counterparts in capacity and bandwidth. The bandwidth limitation of the external memory creates a bottleneck for a large, high-throughput FFT design with large block size. In this paper, we present the Multi-Pass Wide Kernel FFT (MPWK-FFT) architecture for a moderately large block size (32K) with considerations to power consumption and resource usage, as well as throughput. We will also show that the architecture can be easily adapted for different FFT block sizes with different throughput and power requirements. The result is completely contained within an FPGA without relying on external memories. Implementation results are summarized.

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A high-throughput, adaptive FFT architecture for FPGA-based space-borne data processors

This paper presents the results of NASA's game changing technology development entitled “Ultra Low Temperature Electronics” which represents a paradigm shift in spacecraft avionics development. The project has developed compact avionics technologies to address the Command & Data Handling (CDH), Power and Motor Control needs for mission concepts to ocean worlds such as a potential Europa Lander. We addressed this need by developing the key technologies necessary to develop a next generation compact avionics package. The key technologies that we developed significantly reduce the size, weight, power, and cost (SWAP-C) of the avionics package. These technologies will also allow extreme-environment missions to last longer in their environment by reducing the power and energy requirement to keep the avionics warm.

Yutao He

Papers

ISAAC - a case of highly-reusable, highly-capable computing and control platform for radar applications

Optimized FPGA implementation of Multi-Rate FIR filters through Thread Decomposition

Micro-Inspector Avionics Module (MAM): A Self-Contained Low Power, Reconfigurable Avionics Platform for Small Spacecrafts and Instruments

A high-throughput, adaptive FFT architecture for FPGA-based space-borne data processors

Compact low power avionics for the Europa Lander concept and other missions to ocean worlds