Obstacle-avoiding Steiner minimal tree (OASMT) construction has become a focus problem in the physical design of modern very large-scale integration (VLSI) chips. In this article, an effective algorithm is presented to construct an OASMT based on X-architecturex for a given set of pins and obstacles. First, a kind of special particle swarm optimization (PSO) algorithm is proposed that successfully combines the classic genetic algorithm (GA), and greatly improves its own search capability. Second, a pretreatment strategy is put forward to deal with obstacles and pins, which can provide a fast information inquiry for the whole algorithm by generating a precomputed lookup table. Third, we present an efficient adjustment method, which enables particles to avoid all the obstacles by introducing some corner points of obstacles. Finally, an excellent refinement method is discussed to further enhance the quality of the final routing tree, which can improve the quality of the solution by 7.93p on average. To our best knowledge, this is the first time to specially solve the single-layer obstacle-avoiding problem in X-architecture. Experimental results show that the proposed algorithm can further shorten wirelength in the presence of obstacles. And it achieves the best solution quality in a reasonable runtime among the existing algorithms.

Obstacle-Avoiding Algorithm in X-Architecture Based on Discrete Particle Swarm Optimization for VLSI Design

In this paper, we present an algorithm called FOARS for obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) construction. FOARS applies a top-down approach which first partitions the set of pins into several subsets uncluttered by obstacles. Then an obstacle-avoiding Steiner tree is generated for each subset by an obstacle aware version of the rectilinear Steiner minimal tree algorithm FLUTE. Finally, the trees are merged and refined to form the OARSMT. To guide the partitioning of pins, we propose a novel algorithm to construct a linear-sized obstacle-avoiding spanning graph which guarantees to contain a rectilinear minimum spanning tree if there is no obstacle. Experimental results show that FOARS is among the best algorithms in terms of both wirelength and runtime for testcases both with and without obstacles.

/pdf/foars-flute-based-obstacle-avoiding-rectilinear-steiner-tree-457yl2waup.pdf

FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction

A survey on energy-efficient methodologies and architectures of network-on-chip

Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthesis. Local clock skew (LCS) is the clock skew between any two sinks with distance less than or equal to a given threshold. It is defined in the ISPD 2010 High Performance Clock Network Synthesis Contest [1], and it is a novel criterion that captures process variation effects on a clock network. In this paper, we propose a hybrid method that creates a mesh upon a tree topology. Total wire and buffer capacitance is minimized under the LCS and slew constraints. In our method, a clock mesh will be built first according to the positions and capacitance of the sinks. A top-level tree is then built to drive the mesh. A blockage-aware routing method is used during the tree construction. Experimental results show our efficiency and the solution generated by our approach can satisfy the LCS constraint of all the benchmarks in the contest [1], with a fair capacitance usage.

/pdf/local-clock-skew-minimization-using-blockage-aware-mixed-1at6xyne9u.pdf

Local clock skew minimization using blockage-aware mixed tree-mesh clock network

Cross links have been used to reduce skew variations in clock trees. In earlier studies cross links are inserted between the sinks of DC-connected trees. In this paper, we propose a link insertion scheme that inserts cross links between internal nodes of a clock tree. In addition to reducing the skew variability, the proposed approach also reduces the total cross link length. Our work also improves the correlation of sink delays for those sinks within a subtree that have similar path lengths to the cross link. Monte-Carlo (MC) simulations on the ISPD-2010 benchmarks showed that our work could handle variations effectively. In addition to meeting all the design constraints, the solutions produced by our approach have on the average 32% lower capacitance than the least capacitance obtained by the top three teams in the ISPD-2010 design contest [1].

Cross link insertion for improving tolerance to variations in clock network synthesis

In this paper, we present an efficient method to solve the obstacle-avoiding rectilinear Steiner tree problem optimally. Our work is developed based on the GeoSteiner approach, modified and extended to allow rectilinear blockages in the routing region. We extended the proofs on the possible topologies of full Steiner tree (FST) in [4] to allow blockages, where FST is the basic concept used in GeoSteiner. We can now handle hundreds of pins with multiple blockages, generating an optimal solution in a reasonable amount of time. This work serves as a pioneer in providing an optimal solution to this difficult problem.

/pdf/generation-of-optimal-obstacle-avoiding-rectilinear-steiner-2h4i11ensn.pdf

Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree

Power consumption has become a crucial problem in modern circuit design. Multiple supply voltage (MSV) design is introduced to provide higher flexibility in controlling the power and performance tradeoff. One important requirement of MSV design is that timing constraints of the circuit must be satisfied after voltage assignment of the cells. In this article, we develop two algorithms to solve the voltage assignment problem under timing constraints, namely, min-cost flow (MCF) and value-oriented branch-and-bound (VOBB). In the MCF algorithm, the voltage assignment problem is formulated as a convex cost dual network flow problem, and can be solved optimally in polynomial time under certain conditions by calling a MCF solver. The VOBB algorithm, which is a VOBB-based searching method, solves the voltage assignment problem optimally in general cases by employing the MCF algorithm and a linear programming solver as subroutines. At last, we propose a MSV-driven floorplanning framework that optimizes power consumption and physical layout of a circuit simultaneously during the floorplanning stage, by embedding the MCF algorithm into a simulated annealing-based floorplanner and applying the VOBB algorithm as a postprocessing step. We compared our approach with the latest works on this problem, and the experimental results show that, using our approach, significant improvement on power saving can be achieved in much less running time, which confirms the effectiveness and efficiency of our method.

/pdf/msv-driven-floorplanning-hd0l870w5q.pdf

MSV-Driven Floorplanning

One of the sources of “invariance principle” is that the limit properties of the uniform empirical process coincide with that of a Brownian bridge. The deep discussion of limit theorem of the uniform empirical process gathered wild interest of the researchers. In this paper, the precise convergence rate of the uniform empirical process is considered. As is well-known, when 
 
 ε
 
 tends to 0, the precise asymptotic theorems can be demonstrated by referring to the classical method of Gut and Spǎtaru, by using some nice probability inequalities and so on. However, if 
 
 ε
 
 tends to a positive constant, other powerful methods and tools are needed. The method of strong approximation is used in this paper. The main theorems are proved by using the Brownian bridge 
 
 B
 
 
 t
 
 
 
 to approximate the uniform empirical process 
 
 
 
 α
 
 
 n
 
 
 
 
 t
 
 
 
 . The relevant results for the uniform sample quantile process are also presented.

https://downloads.hindawi.com/journals/sp/2022/7649256.pdf

Precise Asymptotics for the Uniform Empirical Process and the Uniform Sample Quantile Process

Core-based system-on-chips (SoCs) fabricated on three-dimensional (3D) technology are emerging for better integration capabilities. Among all available manufactures techniques, 3D SoCs manufactured with die-to-wafer and die-to-die bonding techniques provides higher yield due to its capability of pre-bond test. Effective test architecture design and optimization techniques are essential to minimize the manufacturing cost for such giga-scale integrated circuits. In addition, the prebond test-pin-count constraint during optimization should be carefully considered since these pins occupy large silicon area that cannot be used in functional mode. To address above issues, in this thesis, we first propose novel test access mechanisms solutions for 3D SoCs by our simulated annealing-based technique, considering both testing time and routing cost. In addition, the proposed test-architecture design takes the SoC layout and pre-bond-test-pin into consideration and facilitates the sharing of test wires between pre-bond tests and post-bond test, which significantly reduces the routing cost for a test-access mechanism in 3D technology without violating the test-pin constraint. Afterwards, a thermal-aware test scheduling algorithm is proposed to eliminate the hotspots during test. Experimental results for the ITC’02 SoC benchmarks circuits demonstrate the effectiveness of the proposed solution.

http://www.cs.sjtu.edu.cn/~jiangli/paper/thesis.pdf

Zaichen Qian

Papers

Local clock skew minimization using blockage-aware mixed tree-mesh clock network

Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree

MSV-Driven Floorplanning

Precise Asymptotics for the Uniform Empirical Process and the Uniform Sample Quantile Process

Test Architecture Design and Optimization for Three-Dimensional System-on-chips