Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.

Programmable logic device with cascading DSP slices

An interlace-to-progressive scan conversion system comprises: a spatial line averaging prefilter; a motion estimator; a three-stage adaptive recursive filter. The motion estimator comprises: a 3-D recursive search sub-component having a bilinear interpolator; a motion correction sub-component having an error-function including penalties related to the difference between a given candidate vector and a plurality of neighboring vectors; a block erosion sub-component. The motion estimator assumes that motion is constant between fields. The three-stage adaptive recursive filter comprises: a first stage that selects between using static pixels data and moving pixels data from a next field; a second stage that selects a more valid set of data between motion compensated data from a previous field and the pixels selected by the first stage; a third stage that combines an intra-field interpolation with the more valid set of data selected by the second stage.

Adaptive interlace-to-progressive scan conversion algorithm

Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct a number of external added inputs to the adder. The additional addend inputs can include inputs and outputs cascaded from other arithmetic circuits.

Arithmetic circuit with multiplexed addend inputs

In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.

Applications of cascading DSP slices

A hardware-configurable digital filter (100) is adaptable for providing multiple filtering modes. In one embodiment, the digital filter includes a register-based array (112) of logic circuitry, computational circuitry (114) and mode selection circuitry (110). By reconfiguring data flow within the logic circuitry and the computational circuitry, the mode selection circuitry switches the digital filter between different ones of the multiple filtering modes. Each of the multiplication and addition logic circuits has outputs and inputs selectably coupled to the other of the multiplication and addition logic circuits along a Y direction, with the selectivity being responsive to the mode selection circuitry for arranging the registers as being functionally linear or functionally nonlinear. In a more specific embodiment the filtering modes include polyphase filtering and general purpose filtering applications (such as FIR filtering), and in another more specific embodiment the filtering modes include polyphase direct filtering, polyphase transposed filtering, and at least one general purpose filtering. A specific example application of the above type of digital filter is directed to filtering video pixel components, for example, in resizing a horizontal line of pixels.

Reconfigurable digital filter having multiple filtering modes

A scalable FIR filter architecture that requires fewer computations, less storage registers, and is capable of parallel processing, is presented. The scalable filter architecture reduces the number of computations (e.g., multiplication) by utilizing the inherent symmetry and reduces the number of storage elements required by utilizing what is known as the transpose-form (as compared to direct-form) filter architecture. The filter architecture is scalable to accommodate different complexity levels. In accordance to the present invention, a filter can be scaled up/down by adding/subtracting a processing block to/from the existing structure. Because these processing blocks can process signals independently and simultaneously, the filter architecture in accordance to the present invention allows for parallel and distributive processing thereby meeting the required performance requirements.

Zhao Kan

Papers

Efficient and scalable FIR filter architecture for decimation