Configuration values for Lookup tables (LUTs) and programmable routing switches in an FPGA are provided by means of a number of flip flops arranged in a shift register. This shift register may receive test values in a factory test mode, and operational configuration values (implementing whatever functionality the client requires of the FPGA) in an operational mode. The bitstreams are provided at one end of the shift register, and clocked through until the last flip flop receives its value. Values may also be clocked out at the other end of the shift register to be compared to the initial bitstream in order to identify corruption of stored values e.g. due to radiation exposure. A clock gating architecture is proposed for loading data to or reading data from specific selected shift registers.

System and method for testing and configuration of an fpga

Reconfigurable resource utilisation is a key factor that impacts the performance of reconfigurable instruction set processors (RISPs), which can customise their instruction set for special applications. In this study, the authors propose a novel method to improve reconfigurable resource utilisation of RISPs based on field programmable gate array (FPGA) chips. The method provides a graph multi-colouring allocating algorithm based on a simplified reconfigurable resource model. In the model, they construct three kinds of FPGA-based coarse-grained reconfigurable resources and abstract their attributes mainly through their location and area. The authors’ algorithm employs a graph multi-colouring method to allocate the coarse-grained reconfigurable resources to custom instructions for RISPs. Experimental results demonstrate that their model and algorithm reinforce a state-of-the-art resource utilisation method for RISPs, and reveals some interesting regularities which provide creditable new insights of reconfigurable resource utilisation.

Allocating resources based on a model of coarse-grained reconfigurable architecture

The invention discloses a method for automatic generation of module-level simulation and code configuration of a programmable logic circuit. The method comprises the following steps: analyzing a bottom-layer circuit structure of FPGA, respectively creating configuration addressing models of a bottom-layer circuit and building corresponding module-level code configuration models in combination withsignal connection relations among all layers and all modules of FPGA and SRAM configuration bit information; determining an input port and an output port of a submodule-level circuit through an appointed path in need of simulation and code configuration; determining a path in need of configuration and connection by positioning through the determined input port and the determined output port, finding an SRAM bit in need of configuration and connection according to a module-level code configuration model and outputting an SRAM configuration code stream through an agreed-on output format. With the method, working efficiency of self-simulation and verification of an FPGA chip can be effectively increased. The chip enjoys high expandability and easy troubleshooting operation. The design verification period of the FPGA chip is obviously reduced.

Method and system for automatic generation of module-level simulation and code configuration of programmable logic circuit

The invention discloses a verification method for programmable circuit systems, relates to the technical field of design of programmable integrated circuits, and aims at solving the problem that the verification of the programmable circuit systems is long in time, relatively high in resource occupancy rate of verification environment and relatively low in verification efficiency in the prior art. The verification method for the programmable circuit systems comprises the following steps: establishing a comparison table of circuit function modules and bit stream configuration information; carrying out parameterized function description on each circuit function module according to the comparison table of the circuit function modules and the bit stream configuration information, and carrying out form verification on circuit netlists and the function descriptions of the circuit function modules; carrying out data bit width size setting in the circuit netlists through a configuration control module; and resetting a data sequence and a corresponding address sequence for the corresponding data bit stream in each circuit module according to the generating sequence and the set bit width size. The verification method of the programmable circuit system is suitable for verifying the programmable circuit systems.

Verification method for programmable circuit systems

The invention provides a sparse lookup table and a mapping method of a logic node in FPGA. The sparse lookup table comprise k input ports, a multiplexer, n SRAM units and one output port, wherein the k input ports are connected to k control ends of the multiplexer, the output end of the multiplexer is connected with the output port, n input ends of 2k input ends of the multiplexer are connected with the n SRAM units respectively, and the remaining 2k-n input ends are connected to constant electric levels respectively. According to the sparse lookup table and the mapping method of the logic node in the FPGA, the constant electric levels are utilized to replace partial internal SRAM units, so that the unit area of the sparse lookup table is reduced, and thus the area of the overall FPGA chip can be reduced; meanwhile, through the adoption of a matched mapping algorithm, the chip with lesser area can be utilized to achieve an equivalent subscriber circuit.

Sparse lookup table and mapping method of logic node in FPGA

The invention belongs to the technical field of electronics, and relates to a method for simulating a programmable bit stream file of an FPGA (field programmable gate array) circuit. Multilevel hardware modeling is uniformly performed for functions of an FDP series FPGA device by the aid of a Verilog language, the FPGA device comprises a CLB (configurable logic block), an IOB (input output block), an interconnection resource and the like, simulation and verification can be performed in a commercial tool for Verilog simulation, and programmable data can be downloaded and configured. The circuit function of a programmable logic device can be rapidly verified in the design process of the programmable logic device, an FPGA simulation method is provided for an FPGA user, and the method can be seamlessly connected with FPGA chip design and application circuit design processes. The method can be used for a design stage of an FPGA chip before tape-out, a test stage of the FPGA chip after tape-out and performing simulation and verification on the FPGA bit stream file in the circuit design stage through the FPGA chip by the user, and functional correctness of the FPGA circuit or user circuit is rapidly verified.

Method for FPGA (field programmable gate array) circuit bit stream simulation

With the advantage of making reasonable trade-offs between performance and flexibility, reconfigurable architectures have drawn increasing attention. Automatic tools for mapping applications to reconfigurable architectures, however, are rather complicated and challenging work for the reason that mapping tool is always subject to the specific reconfigurable architecture. In this paper, we explore a general modeling and mapping method for coarse/fine mixed-grained reconfigurable architectures (MGRAs) by reinventing the packing method in traditional FPGA software flow and propose a novel modeling method that can describe both fine and coarse reconfigurable architecture in XML format. After a detailed explanation of our proposed modeling and mapping method, we verify our method by implementing a mapping tool for a reconfigurable architecture and manage to map FFT as an application on it. The experiments demonstrate that our proposed method can be applied to MGRA modeling and mapping and is flexible enough to be extended to other reconfigurable architectures.

A modeling and mapping method for coarse/fine mixed-grained reconfigurable architecture

With the advent of the great challenge brought by increasing complexity of modern large circuit, a pressing and necessary problem, that is, improving the routability and timing performance, is proposed in front of us. A novel packing algorithm called repack based on enhanced packing attraction function is presented while at the same time an iterative CAD flow tool could provide decreased interconnection resources requirement by applying CLB depopulation at given routing channel width limitation and local congested situations. Experimental results show that, for non-iterative flow, compared to the T-VPack and iRAC, repack can achieve 6.4% and 8.1% improvement respectively in timing performance. However, for iterative flow, when compared to T-VPack, repack has 12.6% and 37.6% improvement in area and routing path width respectively. When compared to iRAC, repack has a 0.9% decrease in area, but it has an improvement of 16.2% in routing path width instead.

Zheng Huang

Papers

Method for FPGA (field programmable gate array) circuit bit stream simulation

A modeling and mapping method for coarse/fine mixed-grained reconfigurable architecture

Repack: A packing algorithm to enhance timing and routability of a circuit