Channel coding may be viewed as the best-informed and most potent component of cellular communication systems, which is used for correcting the transmission errors inflicted by noise, interference, and fading. The powerful turbo code was selected to provide channel coding for mobile broad band data in the 3G UMTS and 4G long term evolution cellular systems. However, the 3GPP standardization group has recently debated whether it should be replaced by low density parity check (LDPC) or polar codes in 5G new radio, ultimately reaching the decision to adopt the LDPC code family for enhanced mobile broad band (eMBB) data and polar codes for eMBB control. This paper summarizes the factors that influenced this debate, with a particular focus on the application specific integrated circuit (ASIC) implementation of the decoders of these three codes. We show that the overall implementation complexity of turbo, LDPC, and polar decoders depends on numerous other factors beyond their computational complexity. More specifically, we compare the throughput, error correction capability, flexibility, area efficiency, and energy efficiency of ASIC implementations drawn from 110 papers and use the results for characterizing the advantages and disadvantages of these three codes as well as for avoiding pitfalls and for providing design guidelines.

Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations

In modern communication systems the required data rates are continuously increasing. High speed transmissions can easily generate throughputs far beyond 1 Tbit/s. To ensure error free communication, channel codes like Low-Density Parity Check (LDPC) codes are utilized. However state-of-the-art LDPC decoders can process only data rates in the range of 10 to 50 Gbit/s. This results in a gap in decoder performance which has to be closed. Therefore we propose a new ultra high speed LDPC decoder architecture. We show that our architecture significantly reduces the routing congestion which poses a big problem for fully parallel, high speed LDPC decoders. The presented 65nm ASIC implementation runs at 257 MHz and consumes an area of 12 mm2The resulting system throughput is 160 Gbit/s, it is the fastest LDPC decoder which has been published up to now. At the same time we show that extremely parallel architectures do not only increase the maximum throughput but also increase area and power efficiency in comparison to state-of-the-art decoders.

A new dimension of parallelism in ultra high throughput LDPC decoding

Fractional motion estimation (FME) significantly enhances video compression efficiency, but its high computational complexity also limits the real-time processing capability. In this brief, we present a VLSI implementation of FME design in High Efficiency Video Coding for ultrahigh definition video applications. We first propose a bilinear quarter pixel approximation, together with a search pattern based on it to reduce the complexity of interpolation and fractional search process. Furthermore, a data reuse strategy is exploited to reduce the hardware cost of transform. In addition, using the considered pixel parallelism and dedicated access pattern for memory, we fully pipeline the computation and achieve high hardware utilization. This design has been implemented as a 65-nm CMOS chip and verified. The measured throughput reaches 995 Mpixels/s for $7680\,\times \,4320~30$ frames/s at 188 MHz, at least 4.7 times faster than prior arts. The corresponding power dissipation is 198.6 mW, with a power efficiency of 0.2 nJ/pixel. Due to the optimization, our work achieves more than 52% improvement on power efficiency, relative to previous works in H.264.

High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding

Ultra high definition television (UHDTV) imposes extremely high throughput requirement on video encoders based on High Efficiency Video Coding (H.265/HEVC) and Advanced Video Coding (H.264/AVC) standards. Context-adaptive binary arithmetic coding (CABAC) is the entropy coding component of these standards. In very-large-scale integration implementation, CABAC has known difficulties in being effectively pipelined and parallelized, due to the critical bin-to-bin data dependencies in its algorithm. This paper addresses the throughput requirement of CABAC encoding for UHDTV applications. The proposed optimizations including prenormalization, hybrid path coverage and lookahead rLPS to reduce the critical path delay of binary arithmetic encoding (BAE) by exploiting the incompleteness of data dependencies in rLPS updating. Meanwhile, the number of bins BAE delivers per clock cycle is increased by the proposed bypass bin splitting technique. The context modeling and binarization components are also optimized. As a result, our CABAC encoder delivers an average of 4.37 bins per clock cycle. Its maximum clock frequency reaches 420 MHz when synthesized in 90 nm. The corresponding overall throughput is 1836 Mbin/s that is 62.5% higher than the state-of-the-art architecture.

Ultra-High-Throughput VLSI Architecture of H.265/HEVC CABAC Encoder for UHDTV Applications

This paper presents the first silicon-proven stochastic LDPC decoder to support multiple code rates for IEEE 802.15.3c applications. The critical path is improved by a reconfigurable stochastic check node unit (CNU) and variable node unit (VNU); therefore, a high throughput scheme can be realized with 768 MHz clock frequency. To achieve higher hardware and energy efficiency, the reduced complexity architecture of tracking forecast memory is experimentally investigated to implement the variable node units for IEEE 802.15.3c applications. Based on the properties of parity check matrices and stochastic arithmetic, the optimized routing networks with re-permutation techniques are adopted to enhance chip utilization. Considering the measurement uncertainties, a delay-lock loop with isolated power domain and a test environment consisting of an encoder, an AWGN generator and bypass circuits are also designed for inner clock and information generation. With these features, our proposed fully parallel LDPC decoder chip fabricated in 90-nm CMOS process with 760.3 K gate count can achieve 7.92 Gb/s data rate and power consumption of 437.2 mW under 1.2 V supply voltage. Compared to the state-of-the-art IEEE 802.15.3c LDPC decoder chips, our proposed chip achieves over 90% reduction of routing wires, 73.8% and 11.5% enhancement of hardware and energy efficiency, respectively.

A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications

Structured quasi-cyclic low-density parity-check (QC-LDPC) code is a part of many emerging wireless communication standards, such as WiMAX, WiFi and WPAN. This paper presents a high parallel decoder architecture for the QC-LDPC codes and the corresponding decoder ASIC for WiMAX system. Through utilizing the proposed fully parallel layered scheduling architecture, the decoder chip saves 22.2% memory bits and takes 24∼48 clock cycles per iteration for different code rates. It occupies 3.36 mm2 in SMIC 65nm CMOS, and realizes 1Gbps (1056Mbps) throughput at 1.2V, 110MHz and 10 iterations with the power 115mW and power efficiency 10.9pJ/bit/iteration. The energy/bit/iteration reduces 63.6% in normalized comparison with the state-of-art publication.

A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS

Based on the particular structure of parity check matrix (PCM) of LDPC codes in WiMAX and WiFi wireless communication standards, a new early stopping criterion (SC) is proposed to save the unnecessary decoding iterations. By using the proposed SC, decoding process will be stopped if all the information bits in a code word are corrected even if there are still some errors in the redundant (parity) part. Simulation shows that our proposed SC outperforms previous ones on decoding speed evaluated by average iteration number (AIN) with no bit error rate (BER) performance loss.

An early stopping criterion for decoding LDPC codes in WiMAX and WiFi standards

Permutation network plays an important role in the reconfigurable QC-LDPC decoder for most modern wireless communication systems with multiple code rates and various code lengths. In this paper, we propose the variation Banyan network (VBN) based permutation network architecture for the reconfigurable QC-LDPC decoders and give the control signal generating algorithm for cyclic shift. Through introducing the bypass network, we put forward the nonblocking scheme for any input number and shift number. In addition, the optimized VBN is proposed for WiMAX and WiFi standard, which can shift at most 4 groups of input data, and greatly reduce the hardware complexity. The synthesis results using the 90nm technology demonstrate that the proposed permutation network can be implemented with the gate count of 18.3k and the frequency of 600 MHz.

High parallel variation Banyan network based permutation network for reconfigurable LDPC decoder

In this paper, we propose an ultra high-throughput LDPC decoder SOC to fulfill the requirement of IEEE 802.15.3c standard. By implementing a macro-layer fully parallel architecture, our proposed decoder takes only 4 clock cycles to finish one layered decoding iteration. Interconnection complexity problem introduced by high-parallel decoding is nicely solved by proposed reusable message permutation networks utilizing the features of code PCM. Critical path is shortened by applying frame-level pipeline decoding. A 65nm CMOS chip is fabricated to verify the proposed architecture. Measured at 1.2V, 400MHz and 10 iterations the proposed decoder achieves a data throughput 6.72Gb/s and consumes a power 537.6mW with an energy efficiency 8.0 pJ/bit-iter.

Zhixiang Chen

Papers

High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding

A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS

An early stopping criterion for decoding LDPC codes in WiMAX and WiFi standards

High parallel variation Banyan network based permutation network for reconfigurable LDPC decoder

A macro-layer level fully parallel layered LDPC decoder SOC for IEEE 802.15.3c application