Showing papers by "Zvi Or-Bach published in 1996"
Patent•
15 Mar 1996
TL;DR: In this article, a gate array device, useful either as a configurable gate array or a compact gate array, is described, comprising an array of two-gate logic cells arranged in columns, a metal grid interconnecting said logic cells into clusters of macrocells, and a routing grid comprising parallel metal tracks crossing said columns of logic cells, and wherein no more than two of said parallel metal track are employed to connect to each logic cell.
Abstract: This invention discloses a gate array device, useful either as a configurable gate array device or a compact gate array device, comprising an array of two-gate logic cells arranged in columns, a metal grid interconnecting said logic cells into clusters of macrocells, said grid comprising a bottom metal layer and at least one metal layer disposed over the bottom metal layer, power and ground lines formed of said bottom metal layer, extending generally parallel to said columns and a routing grid interconnecting said clusters of macrocells, said routing grid comprising parallel metal tracks crossing said columns of logic cells, and wherein no more than two of said parallel metal tracks are employed to connect to each logic cell.
49 citations
Patent•
24 Jul 1996
TL;DR: A very high speed customizable logic array device comprising: a substrate having at least one gate layer and at least first, second and third metal layers formed thereon, the gate layer including a multiplicity of identical unit logic cells, the customizable logic arrays device including at least three of the following functionalities: NAND, NOR, inverter, AND and OR and further characterized in that the ratio between the rise time and the fall time of the logic cells embodying each of the at least 3 functionalities is constant.
Abstract: A very high speed customizable logic array device comprising: a substrate having at least one gate layer and at least first, second and third metal layers formed thereon, the gate layer including a multiplicity of identical unit logic cells, the customizable logic array device including at least three of the following functionalities: NAND, NOR, inverter, AND and OR and further being characterized in that the ratio between the rise time and the fall time of the logic cells embodying each of the at least three functionalities is constant.
9 citations