Showing papers by "Actel published in 1986"

User programmable integrated circuit interconnect architecture and test method

Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable elements situated at the intersection of any two segments to be connected. Sensing circuitry and wiring may be included to allow 100% observability of internal circuit nodes, such as module outputs, from an external pad interface.

Programmable low-impedance anti-fuse element

Abstract: An electrically programmable low impedance circuit element is disclosed having capacitor-like structure with very low leakage before programming and a low resistance after programming The electrically programmable low impedance circuit element of the present invention includes a lower conductive electrode which may be formed of a metal or semiconductor material, an insulating layer, which, in a preferred embodiment includes a first layer of silicon dioxide, a second layer of silicon nitride and a third layer of silicon dioxide An upper electrode formed of a metal or of a semiconductor material of the same conductivity type of the lower electrode or a sandwich of both completes the structure

Selectively formable vertical diode circuit element

Abstract: A programmable low impedance interconnect diode element is disclosed having a lower electrode formed of a semiconductor material of a first conductivity type covered by an insulating dielectric layer which may be in a preferred embodiment comprised of an initial layer of silicon dioxide, a second layer of silicon nitride and a third layer of silicon dioxide, covered by a layer of semiconductor material of a second conductivity type A programmable read only memory array and a programmable logic array comprising a plurality of the above-described cells are also disclosed

Central processor architecture implementing deterministic early condition code analysis using digit based, subterm computation and selective subterm combination

Abstract: A central processor architecture implementating a deterministic, digit based, subterm computation and selective subterm combination early condition code analysis mechanism to provide for the early determination of the condition code that will be returned upon normal execution of a condition code setting instruction is described. The early condition code is returned sufficiently early to be combined with a branch mask to substantially reduce if not eliminate the need to interlock an immediately following conditional branch instruction. A wide variety of condition code setting instructions are handled by the deterministic condition code analysis mechanism of the present invention by implementing the mechanism to determine condition codes by the generation of digit subterms of the operand data accompanying condition code setting instruction and then combining the digit subterms in a predetermined manner selected based on the specific condition code setting instruction being executed. Branch decision analysis is performed by inclusion of the branch decision mask as a subterm selectively combined with the condition code subterms.