Showing papers by "Actel published in 2006"

An Analysis of Single Event Upset Dependencies on High Frequency and Architectural Implementations within Actel RTAX-S Family Field Programmable Gate Arrays

Abstract: In order to investigate frequency and architectural effects on Single Event Upset cross sections within RTAX-S FPGA devices, a novel approach to high speed testing is implemented. Testing was performed at variable speeds ranging from 15 MHz to 150 MHz

Biased-Irradiation Characteristics of the Floating Gate Switch in FPGA

Abstract: The radiation characteristic of the floating-gate switch in a 0.22 ?m Flash-based FPGA is investigated by measuring the threshold voltage after each stage of X-ray irradiation. The focus is on the applied bias on the floating-gate device during irradiation. A two-parameter, semi-physical model is used to fit the experimental results. For an erase or write state with a particular irradiation-bias, a set of two fitting parameters can accurately determine the threshold voltage with respect to total radiation dose. The modeling result can be easily integrated into the SPICE simulator for circuit design purposes.

Field programmable gate array including a non-volatile user memory and method for programming

Abstract: An integrated circuit includes a programmable logic unit and an on-chip non-volatile memory. A JTAG port, TAP controller circuit, and program/erase control circuitry provide user access to the non-volatile memory for storage of user data. The non-volatile memory may also be used to store device data such as a serial number, product identification number, date code, or security data. Portions of the non-volatile memory may be made unavailable to the user once programmed, while other portions of the non-volatile may remain available for user access.

A Block-Based Open Source Approach for a Reconfigurable Virtual Instrumentation Platform Using FPGA Technology

Abstract: Recent advances in Field-Programmable Gate Arrays (FPGA) have made it possible to efficiently build various complex hardware emulation systems. This technology promises new levels of system integration onto a single FPGA, but also presents significant challenges to designers. The proposed Reconfigurable Virtual Instrumentation (RVI) project leverages the latest FPGA technological advances. Its goal is to provide a low-cost reusable hardware/software platform for the emulation of multiple electronic and scientific instrumentation systems. Unlike previous approaches, the proposed architecture leverages a block-based design methodology that emphasizes design reuse as an effective mean to cope with the challenge of a growing design complexity. An open source approach to the project allows future contributors to rely on previously developed software, making the emulation of new instruments increasingly more cost-effective. This paper details the architecture of the RVI system with its main building blocks. It also illustrates its capabilities with multiple implementation examples.

Mixed signal system-on-a-chip integrated simultaneous multiple sample/hold circuits and embedded analog comparators

Abstract: An integrated circuit includes a plurality of circuit groups, each circuit group containing a plurality of analog inputs, a buffer, a sample/hold circuit and a comparator. Each buffer has an input to which any of the analog inputs in its group may be programmably connected. The output of each buffer is coupled to the input of the sample/hold circuit in the group. The output of each sample/hold circuit is coupled to one input of a multiplexer. The output of the multiplexer is coupled to the input of an amplifier having programmable gain and programmable offset. The comparator in each group has inputs that may be programmably coupled to at least one analog input in the group or to a reference voltage source.

Processors and FPGAs Quo Vadis

Abstract: Electronic applications continue to demand increased flexibility, configurability, and performance, along with reduced power consumption, board space, and cost. This is increasing pressure to integrate analog, memory, logic, and soft microcontroller unit (MCU) implementations into a single-system chip. As a result, analog, microcontroller, and application-specific integrated circuit (ASIC) suppliers are adding configurability to their product lines. As the race to develop programmable system chip solutions heats up, field-programmable gate array (FPGA) suppliers have a leg up on the competition because programmable logic has proved to be the most difficult of the necessary technologies to master

Power-up and power-down circuit for system-on-a-chip integrated circuit

Abstract: A power-up and power-down circuit for an integrated circuit includes a voltage regulator set for a first voltage. A first I/O pad is coupled internally to an input to the voltage regulator and to first internal circuits. The second voltage is externally coupled to the first I/O pad. A second I/O pad is coupled internally to an output of the voltage regulator configured to drive the base of an external transistor. A third I/O pad of the integrated circuit is coupled internally to a reference-voltage input of the voltage regulator. A fourth I/O pad is coupled to a feedback input of the voltage regulator. A fifth I/O pad of the integrated circuit is coupled internally to logic circuitry that controls power-up and power down of the integrated circuit from internal signals including internal signals from a real-time clock circuit disposed on the integrated circuit.

Post-placement interconnect entropy: how many configuration bits does a programmable logic device need?

Abstract: We introduce the concept of post-placement interconnect entropy: the minimal number of bits required to describe a well-placed netlist, which has connection lengths distributed according to Rent's rule. The entropy is a function of the number N of cells in the netlist and the Rent exponent p. We derive an expression for the entropy per cell and show that it converges as N approaches infinity. The entropy provides an achievable lower bound on the number of configuration bits in a programmable logic device. Specific numerical values are computed for practical situations. For example, any scalable FPGA composed of 4-input lookup table cells would require 31 configuration bits per cell. We compare this to the actual number of configuration bits in a standard FPGA architecture. We generalize the bound to dimensions higher than two, and show that for any p there is an optimal dimension that minimizes the bound.

Mixed-signal system-on-a-chip analog signal direct interconnection through programmable logic control

Abstract: A programmable analog circuit includes a plurality of analog inputs, a differential analog buffer, a digital-to-analog converter, an analog-to-digital converter, and an operational amplifier having an inverting input and a non-inverting input. An analog switching network is coupled between the plurality of analog inputs, the differential analog buffer, the digital-to-analog converter, the analog-to-digital converter, and the operational amplifier and is configured to allow programmable connections from any of the plurality of analog inputs, the differential analog buffer, and the digital-to-analog converter to the inverting input and a non-inverting input; of the operational amplifier. An array of programmable logic is programmably coupled to the input to the digital-to-analog converter and the output of the analog-to-digital converter.

Modeling the Effects of Input Slew Rate and Temporal Proximity of Input Transitions in Event-Driven Simulation

Abstract: This paper presents a new approach to improve the speed of switch-level timing simulation of MOS digital circuits. High performance is achieved by redefining the concept of event within the event-driven selective-trace paradigm. Unlike conventional techniques, in our approach an event occurs on an input slope change rather than a voltage change, thereby, lessening significantly the number of events to be treated during the simulation. The accuracy of this approach is improved by taking into account temporal proximity of multiple input transitions. Experimental results obtained for several circuits show significant speed-up compared to conventional switch-level timing simulation techniques

Post-placement interconnect entropy

Abstract: We introduce the concept of post-placement interconnect entropy: the minimal number of bits required to describe a well-placed netlist, which has connection lengths distributed according to Rent's rule. The entropy is a function of the number N of cells in the netlist and the Rent exponent p. We derive an expression for the entropy per cell and show that it converges as N approaches infinity. The entropy provides an achievable lower bound on the number of configuration bits in a programmable logic device. Specific numerical values are computed for practical situations. For example, any scalable FPGA composed of 4-input lookup table cells would require 31 configuration bits per cell. We compare this to the actual number of configuration bits in a standard FPGA architecture. We generalize the bound to dimensions higher than two, and show that for any p there is an optimal dimension that minimizes the bound.

Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop

Abstract: A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.

Method for erasing programmable interconnect cells for field programmable gate arrays using reverse bias voltage

Abstract: A method for erasing a non-volatile memory cell interconnect switch in an FPGA comprised providing an FPGA having a core containing a plurality of non-volatile-memory-cell interconnect switches, each switch formed in a switch well region and coupled to a source/drain of an n-channel transistor formed in a grounded well region separate from the switch well region. A non-volatile memory cell interconnect switch is selected for erasing. The switch well region is disconnected from ground. A VCC potential is applied to the switch well region and to the drain of the n-channel transistor to which it is coupled and an erase potential is applied to the gate of the selected non-volatile memory cell interconnect switch.